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motorola semiconductor advance information DSP56366 order this document by: DSP56366/d rev 1.3 12/01 ? 2000, 2001 motorola, inc. advance infomation this document contains information on a new product. specifications and information herein are subject to change without notice . advance information 24-bit audio digital signal processor the DSP56366 supports digital audio applications requ iring sound field processing, acoustic equalization, and other digital audio algorithms. the DSP56366 uses the high performance, single-clock-per-cycle dsp56300 core family of programmable cmos digita l signal processors (dsps) combined with the audio signal processing capability of the moto rola symphony? dsp family, as shown in figure 1 . this design provides a two-fold performance increase over moto rola?s popular symphony family of dsps while retaining code compatibility. signif icant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, an d direct memory access (dma). the DSP56366 offers 120 million instructions per second (mips) using an internal 120 mhz clock at 3.3 v. figure 1 DSP56366 block diagram clock generator internal data bus extal program ram /instr. cache 3k x 24 program rom 40k x 24 bootstrap rom program interrupt controll er program decode controlle program address generator ya b xab pab ydb xdb pdb gdb moda/irqa modb/irqb data alu 24x24 + 56 -> 56-bit mac two 56-bit accumulators barrel shifter modc/irqc pll once? host inter- face dax (spdif tx.) inter- face 4 16 x memory ram 13k x 24 rom 32k x 24 y memory ram 7k x 24 rom 8k x 24 ddb dab six channels dma unit memory expansion area peripheral ym_eb xm_eb pm_eb pio_eb 24 bits bus expansion area jtag 4 5 reset power mngmnt pinit/nmi 2 triple timer 1 modd/irqd dram & sram bus interface & i - cache external address bus switch external data bus switch address 10 data control 24 18 esai inter- face 8 6 esai_1 address generation unit 24-bit dsp56300 core shi inter- face
ii DSP56366 advance information motorola section 1 signal/connection descriptions . . . . . . . . . . . . . . . . . . . . . . . . 1-1 section 2 specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 section 3 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 section 4 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 section 5 ordering informat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 appendix a power consumption benchmark . . . . . . . . . . . . . . . . . . . . . . . . a-1 appendix b ibis model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i- 1 for technical assistance: tel ephone: 1-800-521-6274 email: dsphelp@dsp.sps.mot.com internet: http://www.motorola-dsp.com data sheet conventions this data sheet uses the following conventions: overbar used to indicate a signal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (act ive high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true ( active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol note: values for v il , v ol , v ih , and v oh are defined by individual product specifications. table of contents
DSP56366 features advance information motorola DSP56366 iii features dsp56300 modular chassis ? 120 million instructions per second (m ips) with an 120 mhz clock at 3.3v. ? object code compatible with the 56k core. ? data alu with a 24 x 24 bit multiplier-accumula tor and a 56-bit barrel sh ifter. 16-bit arithmetic support. ? program control with positio n independent code support an d instruction cache support. ? six-channel dma controller. ? pll based clocking with a wide ra nge of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2 i : i=0 to 7). reduces clock noise. ? internal address tracing support and once ? for hardware/software debugging. ? jtag port. ? very low-power cmos design, fully static d esign with operating frequencies down to dc. ? stop and wait low-power standby modes. on-chip memory configuration ? 7kx24 bit y-data ram and 8kx24 bit y-data rom. ? 13kx24 bit x-data ram an d 32kx24 bit x-data rom. ? 40kx24 bit program rom. ? 3kx24 bit program ram and 192x24 bit bootstra p rom. 1k of program ram may be used as instruction cache or fo r program rom patching. ? 2kx24 bit from y data ram and 5kx24 bit from x data ram can be switched to program ram resulting in up to 10kx24 bit of program ram. off-chip memory expansion ? external memory expansion port. ? off-chip expansion up to two 16m x 24-bit word of data memory. ? off-chip expansion up to 16m x 24 -bit word of program memory. ? simultaneous glueless interface to sram and dram.
advance information iv DSP56366 motorola DSP56366 features peripheral modules ? serial audio interface (esai): up to 4 receiver s and up to 6 transmitters, master or slave. i 2 s, sony, ac97, network and other programmable protocols. ? serial audio interface i(esai_1): up to 4 receiver s and up to 6 transmitters , master or slave. i 2 s, sony, ac97, network and other programmable protocols the esai_1 shares four of the data pins with esai, and esai_1 does not support hckr and hckt (high frequency clocks) ? serial host interface (shi): spi and i 2 c protocols, multi master capability, 10-word receive fifo, support for 8, 16 and 24-bit words. ? byte-wide parallel host inte rface (hdi08) with dma support. ? triple timer module (tec). ? digital audio transmitter (dax): 1 serial transmitte r capable of supporting the spdif, iec958, cp- 340 and aes/ebu digital audio formats. ? pins of unused peripherals (except shi) may be programmed as gpio lines. 144-pin plastic tqfp package. documentation table 1 lists the documents that provide a complete descrip tion of the DSP56366 and are required to design properly with the part. documentation is available from a loca l motorola distributor, a motorola semiconductor sales office, a motorola literature di stribution center, or through the motorola dsp home page on the internet (the sour ce for the latest information). table 1 DSP56366 documentation document name description order number dsp56300 family manual detailed description of the 56000-family architecture and the 24-bit core processor and instruction set dsp56300fm/ad DSP56366 user?s manual detailed desc ription of memory, peripherals, and interfaces DSP56366um/d DSP56366 technical data sheet electrical and timing specifications; pin and package descriptions DSP56366/d DSP56366 product brief brief desc ription of the chip DSP56366p/d
motorola DSP56366 advance information 1-1 section 1 signal/connection descriptions signal groupings the input and output signals of the DSP56366 are organized into functional groups, which are listed in table 1-1 and illustrated in figure 1-1 . the DSP56366 is operated from a 3.3 v supply; however , some of the inputs can tolerate 5 v. a special notice for this feature is added to th e signal descriptions of those inputs. table 1-1 DSP56366 functional signal groupings functional group number of signals detailed description power (v cc ) 20 table 1-2 ground (gnd) 18 table 1-3 clock and pll 3 table 1-4 address bus port a 1 18 table 1-5 data bus 24 table 1-6 bus control 10 table 1-7 interrupt and mode control 5 table 1-8 hdi08 port b 2 16 table 1-9 shi 5 table 1-10 esai port c 3 12 table 1-11 esai_1 port e 5 6 table 1-12 digital audio transmitter (dax) port d 4 2 table 1-13 timer 1 table 1-14 jtag/once port 4 table 1-15
1-2 DSP56366 advance information motorola signal/connection descriptions signal groupings notes: 1. port a is the external memory interface port, including the external a ddress bus, data bus, and control signals. 2. port b signals are the gpio port signals wh ich are multiplexed with the hdi08 signals. 3. port c signals are the gpio port signals wh ich are multiplexed with the esai signals. 4. port d signals are the gpio port signals which are multiplexed with the dax signals. 5. port e signals are the gpio port signals wh ich are multiplexed with the esai_1 signals. table 1-1 DSP56366 functional signal groupings (continued) functional group number of signals detailed description
signal/connection descriptions signal groupings motorola DSP56366 advance information 1-3 figure 1-1 signals identified by functional group port a address bus a0-a17 vcca (3) gnda (4) d0-d23 vccd (4) gndd (4) aa0-aa2/ras0 -ras 2 port a bus control port a data bus once ? on-chip emulation/ tck tdo vcch gndh vccql (4) port b port c jtag port pinit/nmi vccqh (3) vccc (2) gndc (2) interrupt and mode control moda/irqa modb/irqb modc/irqc modd/irqd reset pll and clock extal pcap gndp vccp port d quiet power gndq (4) spdif transmitter (dax) ado [pd1] aci [pd0] timer 0 tio0 [tio0] hreq sck/scl miso/sda ss /ha2 mosi/ha0 tms parallel host port (hdi08) DSP56366 had(7:0) [pb0-pb7] has/ha0 [pb8] ha8/ha1 [pb9] ha9/ha2 [pb10] hrw/hrd [pb11] hds/hwr [pb12] hcs/ha10 [pb13] horeq/htrq [pb14] hack/hrrq [pb15] serial audio interface (esai) tdi serial host interface (shi) gnds (2) vccs (2) fst [pc4] hckt [pc5] sckr [pc0] fsr [pc1] hckr [pc2] sdo0[pc11] / sdo0_1[pe11] sdo1[pc10] / sdo1_1[pe10] sdo2/sdi3[pc9] / sdo2_1/sdi3_1[pe9] sdo3/sdi2[pc8] / sdo3_1/sdi2_1[pe8] sdo4/sdi1 [pc7] sdo5/sdi0 [pc6] fs sckt_1[pe3] sckt[pc3] t_1[pe4] sckr_1[pe0] fsr_1[pe1] sdo4_1/sdi1_1[pe7] sdo5_1/sdi0_1[pe6] bb bg br ta wr rd cas port e serial audio interface(esai_1)
1-4 DSP56366 advance information motorola signal/connection descriptions power power ground table 1-2 power inputs power name description v ccp pll power ?v ccp is v cc dedicated for pll use. the voltage should be well-regulated and the input should be provided with an extrem ely low impedance path to the v cc power rail. there is one v ccp input. v ccql (4) quiet core (low) power? v ccql is an isolated power for the internal processing logic. this input must be tied externally to all other chip power inputs. the user must provide ade quate external decoupling capacitors. there are four v ccql inputs. v ccqh (3) quiet external (high) power ?v ccqh is a quiet power source for i/o lines. this input must be tied externally to all other chip power inputs. the user must provide adequa te decoupling capacitors. there are three v ccqh inputs. v cca (3) address bus power ?v cca is an isolated power for sections of the address bus i/o drivers. this input must be tied externally to all othe r chip power inputs. the user must provide adequate external decoupling capacitors. there are three v cca inputs. v ccd (4) data bus power ?v ccd is an isolated power for se ctions of the data bus i/o dr ivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are four v ccd inputs. v ccc (2) bus control power ?v ccc is an isolated power for the bus contro l i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate exte rnal decoupling capacitors. there are two v ccc inputs. v cch host power ?v cch is an isolated power for the hdi08 i/o driver s. this input must be tied externally to all other chip power inputs. the user must provide ad equate external decoupling capacitors. there is one v cch input. v ccs (2) shi, esai, esai_1, dax and timer power ?v ccs is an isolated power for the shi, esai, esai_1, dax and timer. this input mu st be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are two v ccs inputs. table 1-3 grounds ground name description gnd p pll ground ?gnd p is a ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.47 f capacitor located as close as possible to the chip package. there is one gnd p connection.
signal/connection descriptions clock and pll motorola DSP56366 advance information 1-5 clock and pll gnd q (4) quiet ground ?gnd q is an isolated ground for the internal pr ocessing logic. this connection must be tied externally to all other chip ground connections. the user must pr ovide adequate ex ternal decoupling capacitors. there are four gnd q connections. gnd a (4) address bus ground ?gnd a is an isolated ground for sections of the address bus i/o drivers. this connection must be tied ex ternally to all other chip ground connect ions. the user must provide adequate external decoupling capacitors. there are four gnd a connections. gnd d (4) data bus ground ?gnd d is an isolated ground for sections of th e data bus i/o drivers. this connection must be tied externally to all other chip ground c onnections. the user must pr ovide adequate external decoupling capacitors. there are four gnd d connections. gnd c (2) bus control ground ?gnd c is an isolated ground for the bus cont rol i/o drivers. this connection must be tied externally to all other chip ground connect ions. the user must provi de adequate external decoupling capacitors. there are two gnd c connections. gnd h host ground ?gnd h is an isolated ground for the hd08 i/o dr ivers. this connection must be tied externally to all other chip gr ound connections. the user must provi de adequate exte rnal decoupling capacitors. there is one gnd h connection. gnd s (2) shi, esai, esai_1, dax and timer ground ?gnd s is an isolated ground for the shi, esai, esai_1, dax and timer. this connection must be tied externally to all othe r chip ground connections. the user must provide ade quate external decoupling ca pacitors. there are two gnd s connections. table 1-4 clock and pll signals signal name type state during reset signal description extal input input external clock input ?an external clock source must be connected to extal in order to supply the clock to the internal clock ge nerator and pll. this input cannot tolerate 5 v . pcap input input pll capacitor ?pcap is an input connecting an of f-chip capacitor to the pll filter. connect one capacitor te rminal to pcap and the other terminal to v ccp . if the pll is not used, pcap may be tied to v cc , gnd, or left floating. pinit/nmi input input pll initial/nonmaskable interrupt ?during assertion of reset , the value of pinit/nmi is written into the pll enable (pen) bit of the pll control register, determining whether the pll is en abled or disabled. after reset de assertion and during normal instruction processing, the pinit/nmi schmitt-trigger input is a negative-edge-triggered nonmas kable interrupt (nmi) request internally synchronized to internal system clock. this input cannot tolerate 5 v . table 1-3 grounds ground name description
1-6 DSP56366 advance information motorola signal/connection descriptions external memory expansion port (port a) external memory expansion port (port a) when the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and tri- states the relevant port a signals: a0?a17, d0?d23, aa0/ras0 ?aa2/ras2 , rd , wr , bb , cas . external address bus external data bus external bus control table 1-5 external address bus signals signal name type state during reset signal description a0?a17 outpu t tri-stated address bus ?when the dsp is the bus mast er, a0?a17 are active-high outputs that specify the address for external program and data memory accesses. otherwise, the signals are tri-stated. to minimize power diss ipation, a0?a17 do not change state when external me mory spaces are not being accessed. table 1-6 external data bus signals signal name type state during reset signal description d0?d23 input/output tri-stated data bus ?when the dsp is the bus master, d0?d23 are active- high, bidirectional input /outputs that provide th e bidirectional data bus for external program and data memory accesses. otherwise, d0?d23 are tri-stated. table 1-7 external bus control signals signal name type state during reset signal description aa0?aa2/ ras0 ? ras2 outpu t tri-stated address attribute or row address strobe ?when defined as aa, these signals can be used as chip selects or additiona l address lines. when defined as ras , these signals can be used as ras for dram interface. these signals are tri-statable outputs with programmable polarity.
signal/connection descriptions external memory expansion port (port a) motorola DSP56366 advance information 1-7 cas outpu t tri-stated column address strobe ? when the dsp is the bus master, cas is an active-low output used by dram to strobe the column address. otherwise, if the bus mastership enable (bme) bit in the dram control register is cleared, the signal is tri-stated. rd outpu t tri-stated read enable ?when the dsp is the bus master, rd is an active-low output that is asserted to read external memory on the data bus (d0-d23). otherwise, rd is tri- stated. wr outpu t tri-stated write enable ?when the dsp is the bus master, wr is an active-low output that is asserted to write external memory on the data bus (d0-d23). otherwise, wr is tri- stated. ta input ignored input transfer acknowledge ?if the dsp is the bus master and there is no external bus activity, or the dsp is not the bus master, the ta input is ignored. the ta input is a data transfer acknowledge (dtack) function that can extend an external bus cycle indefinitely. any number of wait states (1 , 2. . .infinity) may be added to the wait states inserted by the bcr by keeping ta deasserted. in t ypical operation, ta is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. the current bus cycle completes one clock period after ta is asserted synchronous to the inte rnal system clock. the number of wait states is determined by the ta input or by the bus control register (bcr), whichever is longer. the bcr can be used to set the minimum numbe r of wait states in external bus cycles. in order to use the ta functionality, the bcr must be programmed to at least one wait state. a zero wait state access cannot be extended by ta deassertion, otherwise improper operation may result. ta can operate synchronously or asynchronously, depending on the setting of the tas bit in the operating mode register (omr). ta functionality may not be used while pe rforming dram type accesses, otherwise improper operation may result. br outpu t output (deasserted ) bus request ?br is an active-low output, never tri-stated. br is asserted when the dsp requests bus mastership. br is deasserted when the dsp no longer needs the bus. br may be asserted or deasserted inde pendent of whether the DSP56366 is a bus master or a bus slave. bus ?parking? allows br to be deasserted even though the DSP56366 is the bus master. (see the de scription of bus ?parking? in the bb signal description.) the bus request hold (brh) bi t in the bcr allows br to be asserted under software control even though the dsp does not need the bus. br is typically sent to an external bus arbitrator that cont rols the priority, parking, and tenure of each master on the same external bus. br is only affected by dsp requests for the external bus, never for the internal bus. during hardware reset, br is deasserted and the arbitration is reset to the bus slave state. table 1-7 external bus control signals (continued) signal name type state during reset signal description
1-8 DSP56366 advance information motorola signal/connection descriptions interrupt and mode control interrupt and mode control the interrupt and mode control signal s select the chip?s operating mode as it comes out of hardware reset. after reset is deasserted, these inputs ar e hardware interrupt request lines. bg input ignored input bus grant ?bg is an active-low input. bg is asserted by an external bus arbitration circuit when the DSP56366 becomes the next bus master. when bg is asserted, the DSP56366 must wait until bb is deasserted before ta king bus mastership. when bg is deasserted, bus mastership is typically given up at the end of the current bus cycle. this may occur in the middle of an instructi on that requires more than one external bus cycle for execution. for proper bg operation, the asynchronous bus ar bitration enable bit (abe) in the omr register must be set. bb input/ outpu t input bus busy ?bb is a bidirectional ac tive-low i nput/output. bb indicates that the bus is active. only after bb is deasserted can the pending bu s master become the bus master (and then assert the signal agai n). the bus master may keep bb asserted after ceasing bus activity regardless of whether br is asserted or deassert ed. this is called ?bus parking? and allows the curre nt bus master to reuse the bus without rear bitration until another device requires the bus. the deassertion of bb is done by an ?active pull-up? method (i.e., bb is driven high and then released and held high by an external pull-up resistor). for proper bb operation, the asynchronous bus arbi tration enable bit (abe) in the omr register must be set. bb requires an external pull-up resistor. table 1-7 external bus control signals (continued) signal name type state during reset signal description
signal/connection descriptions interrupt and mode control motorola DSP56366 advance information 1-9 table 1-8 interrupt and mode control signal name type state during reset signal description moda/irqa input input mode select a/external interrupt request a? moda/irqa is an active-low schmitt-trigger input, inte rnally synchronized to the dsp clock. moda/irqa selects the initial chip operating m ode during hardware reset and becomes a level-sensitive or negative-edge-triggered, mask able interrupt request inpu t during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into th e omr when the reset signal is deasserted. if the processor is in the stop standby state and the moda/irqa pin is pulled to gnd, the processor will exit the stop state. this input is 5 v tolerant . modb/irqb input input mode select b/external interrupt request b? modb/irqb is an active-low schmitt-trigger input, inte rnally synchronized to the dsp clock. modb/irqb selects the initial chip operating m ode during hardware reset and becomes a level-sensitive or negative-edge-triggered, mask able interrupt request inpu t during normal instruction processing. moda, modb, modc, and modd se lect one of 16 in itial chip operating modes, latched into omr when the reset signal is deasserted. this input is 5 v tolerant. modc/irqc input input mode select c/external interrupt request c? modc/irqc is an active-low schmitt-trigger input, inte rnally synchronized to the dsp clock. modc/irqc selects the initial chip operating m ode during hardware reset and becomes a level-sensitive or negative-edge-triggered, mask able interrupt request inpu t during normal instruction processing. moda, modb, modc, and modd se lect one of 16 in itial chip operating modes, latched into omr when the reset signal is deasserted. this input is 5 v tolerant. modd/irqd input input mode select d/external interrupt request d ?modd/irqd is an active-low schmitt-trigger input, inte rnally synchronized to the dsp clock. modd/irqd selects the initial chip operating m ode during hardware reset and becomes a level-sensitive or negative-edge-triggered, mask able interrupt request inpu t during normal instruction processing. moda, modb, modc, and modd se lect one of 16 in itial chip operating modes, latched into omr when the reset signal is deasserted. this input is 5 v tolerant. reset input input reset? reset is an active-low , schmitt-trigger input. when asserted, the chip is placed in the reset state and the internal phase generator is rese t. the schm itt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, m odc, and modd inputs. the reset signal must be asserted during power up. a stable ex tal signal must be supplied while reset is being asserted. this input is 5 v tolerant .
1-10 DSP56366 advance information motorola signal/connection descriptions parallel host interface (hdi08) parallel host interface (hdi08) the hdi08 provides a fast, 8-bit, para llel data port that may be connected directly to the host bus. the hdi08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, dsps, and dma hardware.
signal/connection descriptions parallel host interface (hdi08) motorola DSP56366 advance information 1-11 table 1-9 host interface signal name type state during reset signal description h0?h7 input/ output host data? when hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is select ed, these signals are lines 0?7 of the bidirectional, tri-state data bus. had0?had7 input/ output host address/data? when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, these signals are lines 0?7 of the address/data bidirectional, multip lexed, tri-state bus. pb0?pb7 input, output, or disconnected gpio disconnected port b 0?7 ?when the hdi08 is configured as gpio, these signals are individually programmable as input, output, or in ternally disconnected. the default state after reset for th ese signals is gpio disconnected. these inputs are 5 v tolerant. ha0 input gpio disconnected host address input 0 ?when the hdi08 is programmed to interface a nonmultiplexed host bus and the hi func tion is selected, this signal is line 0 of the host address input bus. has/ has input host address strobe? when hdi08 is programmed to interface a multiplexed host bus and th e hi function is selected, this signal is the host address strobe (has) schmitt-trigger input. the polarity of the address strobe is programma ble, but is configured active-low (has ) following reset. pb8 input, output, or disconnected port b 8 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gp io disconnected. this input is 5 v tolerant. ha1 input gpio disconnected host address input 1 ?when the hdi08 is programmed to interface a nonmultiplexed host bus and the hi func tion is selected, this signal is line 1 of the host address (ha1) input bus. ha8 input host address 8 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected , this signal is line 8 of the host address (ha8) input bus. pb9 input, output, or disconnected port b 9 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gp io disconnected. this input is 5 v tolerant.
1-12 DSP56366 advance information motorola signal/connection descriptions parallel host interface (hdi08) ha2 input gpio disconnected host address input 2 ?when the hdi08 is programmed to interface a non-multiplexed host bus and the hi func tion is selected, this signal is line 2 of the host address (ha2) input bus. ha9 input host address 9 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected , this signal is line 9 of the host address (ha9) input bus. pb10 input, output, or disconnected port b 10 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hrw input gpio disconnected host read/write ?when hdi08 is programmed to interface a single- data-strobe host bus and the hi function is selected, this signal is the host read/write (hrw) input. hrd / hrd input host read data ?when hdi08 is programmed to interface a double- data-strobe host bus and the hi function is selected, this signal is the host read data strobe (hrd) schmitt-tri gger input. the polarity of the data strobe is programmabl e, but is configured as active-low (hrd ) after reset. pb11 input, output, or disconnected port b 11 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hds / hds input gpio disconnected host data strobe? when hdi08 is programmed to interface a single- data-strobe host bus and the hi function is selected, this signal is the host data strobe (hds) schmitt- trigger input. the polarity of the data strobe is programmable, but is confi gured as active-low (hds ) following reset. hwr / hwr input host write data ?when hdi08 is programmed to interface a double- data-strobe host bus and the hi function is selected, this signal is the host write data strobe (hwr) schmitt-trigger input. th e polarity of the data strobe is programmable, but is configured as active-low (hwr ) following reset. pb12 input, output, or disconnected port b 12 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. table 1-9 host interface (continued) signal name type state during reset signal description
signal/connection descriptions parallel host interface (hdi08) motorola DSP56366 advance information 1-13 hcs input gpio disconnected host chip select? when hdi08 is programmed to interface a nonmultiplexed host bus and the hi func tion is selected, this signal is the host chip select (hcs) input. the polarity of the chip select is programmable, but is conf igured active-low (hcs ) after reset. ha10 input host address 10 ?when hdi08 is programmed to interface a multiplexed host bus and the hi functi on is selected, this signal is line 10 of the host address (ha10) input bus. pb13 input, output, or disconnected port b 13 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gp io disconnected. this input is 5 v tolerant. horeq / horeq output gpio disconnected host request ?when hdi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host request (horeq) output. the pol arity of the host request is programmable, but is confi gured as active-low (horeq ) following reset. the host request may be programmed as a driven or open-drain output. htrq / htrq output transmit host request? when hdi08 is programmed to interface a double host request host bus and the hi f unction is selected, this signal is the transmit host request (htrq) out put. the polarity of the host request is programmable, but is configured as active-low (htrq ) following reset. the host request may be programmed as a driven or open-drain output. pb14 input, output, or disconnected port b 14 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gp io disconnected. this input is 5 v tolerant. table 1-9 host interface (continued) signal name type state during reset signal description
1-14 DSP56366 advance information motorola signal/connection descriptions parallel host interface (hdi08) hack / hack input gpio disconnected host acknowledge ?when hdi08 is programmed to interface a single host request host bus and th e hi function is selected, this signal is the host acknowledge (hack) schmitt-trigge r input. the polarity of the host acknowledge is programmabl e, but is configured as active-low (hack ) after reset. hrrq / hrrq output receive host request ?when hdi08 is programmed to interface a double host request host bus and the hi function is selected , this signal is the receive host request (hrrq) output. the polarity of the host request is programmable, but is confi gured as active-low (hrrq ) after reset. the host request may be programmed as a driven or open-drain output. pb15 input, output, or disconnected port b 15 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. table 1-9 host interface (continued) signal name type state during reset signal description
signal/connection descriptions serial host interface motorola DSP56366 advance information 1-15 serial host interface the shi has five i/o signals that can be configured to allow the shi to operate in either spi or i 2 c mode. table 1-10 serial host interface signals signal name signal type state during reset signal description sck input or output tri- stated spi serial clock ?the sck signal is an output wh en the spi is configured as a master and a schmitt-trigger input when the spi is config ured as a slave. when the spi is configured as a master, the sck si gnal is derived from th e internal shi clock generator. when the spi is c onfigured as a slave, the sc k signal is an input, and the clock signal from the external master synchr onizes the data transfer. the sck signal is ignored by the spi if it is define d as a slave and the slave select (ss ) signal is not asserted. in both the master and slave spi devi ces, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi transfer protocol. scl input or output i 2 c serial clock ?scl carries the clock for i 2 c bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a sl ave and an open-drain output when configured as a master. scl should be connected to v cc through a pull-up resistor. this signal is tri-stated during hardware, so ftware, and individual re set. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant. miso input or output tri- stated spi master-in-slave-out ?when the spi is configured as a master, miso is the master data input line. the miso signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when configured for the spi slave mode, and tri-stated if configured for the spi slave mode when ss is deasserted. an external pull-up resistor is not required for spi operation. sda input or open-drain output i 2 c data and acknowledge ?in i 2 c mode, sda is a schmi tt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v cc through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is hi gh in the case of start and stop events. a high-to-low transition of the sda line while scl is high is a unique situation, and is defined as the start event. a low-to-high transition of sda while scl is high is a unique situation define d as the stop event. this signal is tri-stated during hardware, so ftware, and individual re set. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant.
1-16 DSP56366 advance information motorola signal/connection descriptions serial host interface mosi input or output tri- stated spi master-out-slave-in ?when the spi is configured as a master, mosi is the master data output li ne. the mosi signal is used in conjunction with the miso signal for transmitting and receiving se rial data. mosi is the slav e data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode. ha0 input i 2 c slave address 0 ?this signal uses a schmitt-tri gger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when configured for the i 2 c master mode. this signal is tri-stated duri ng hardware, software, and indi vidual reset. t hus, there is no need for an external pull-up in this state. this input is 5 v tolerant. ss input tri- stated spi slave select ?this signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for transfer. when conf igured for the spi master mode, this signal should be kept deasserted ( pulled high). if it is asserted while configured as spi master, a bus error condition is flagged. if ss is deasserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. ha2 input i 2 c slave address 2 ?this signal uses a schmitt-tri gger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. this signal is tri-stated duri ng hardware, software, and indi vidual reset. t hus, there is no need for an external pull-up in this state. this input is 5 v tolerant . hreq input or output tri- stated host request ?this signal is an active low schmitt-trigger input when configured for the master mode but an active low outpu t when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next data word transfer and de asserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input. when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing the data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. this signal is tri-stated during hardware, software, pe rsonal reset, or when the hreq1?hreq0 bits in the hcsr are cleared. there is no need for external pull-up in this state. this input is 5 v tole rant. table 1-10 serial host interface signals (continued) signal name signal type state during reset signal description
signal/connection descriptions enhanced serial audio interface motorola DSP56366 advance information 1-17 enhanced serial audio interface table 1-11 enhanced serial audio interface signals signal name signal type state during reset signal description hckr input or output gpio disconnected high frequency clock for receiver ?when programmed as an input, this signal provides a high frequency cloc k source for the esai receiver as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high-frequency samp le clock (e.g., for external digital to analog converters [dacs]) or as an additiona l system clock. pc2 input, output, or disconnected port c 2 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. hckt input or output gpio disconnected high frequency clock for transmitter ?when programmed as an input, this signal provides a high frequency cl ock source for the esai transmitter as an alternate to the dsp core cloc k. when programmed as an output, this signal can serve as a high frequency sa mple clock (e.g., for external dacs) or as an additional system clock. pc5 input, output, or disconnected port c 5 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. fsr input or output gpio disconnected frame sync for receiver ?this is the receiver frame sync input/output signal. in the asynchronous mode (syn= 0), the fsr pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmitter exte rnal buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direc tion is determined by the rfsd bit in the rccr register. wh en configured as the output flag of1, this pin will reflect the value of the of1 bit in the saicr register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc1 input, output, or disconnected port c 1 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant.
1-18 DSP56366 advance information motorola signal/connection descriptions enhanced serial audio interface fst input or output gpio disconnected frame sync for transmitter ?this is the transmi tter frame sync input/ output signal. for synchronous mode, th is signal is the frame sync for both transmitters and receivers. for async hronous mode, fst is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direction (tfsd) bit in the esai transmit clock control register (tccr). pc4 input, output, or disconnected port c 4 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sckr input or output gpio disconnected receiver serial clock ?sckr provides the receiver serial bit clock for the esai. the sckr operates as a clock input or output used by all the enabled receivers in the asynchronous m ode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direc tion is determined by the rckd bit in the rccr register. when configured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc0 input, output, or disconnected port c 0 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sckt input or output gpio disconnected transmitter serial clock ?this signal provides the serial bit rate clock for the esai. sckt is a clock input or output used by all enabled transmitters and receivers in sync hronous mode, or by all enabled transmitters in asynchronous mode. pc3 input, output, or disconnected port c 3 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. table 1-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
signal/connection descriptions enhanced serial audio interface motorola DSP56366 advance information 1-19 sdo5 output gpio disconnected serial data output 5 ?when programmed as a tran smitter, sdo5 is used to transmit data from the tx5 serial transmit shift register. sdi0 input serial data input 0 ?when programmed as a receiver, sdi0 is used to receive serial data into the rx0 serial receive shift register. pc6 input, output, or disconnected port c 6 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo4 output gpio disconnected serial data output 4 ?when programmed as a tran smitter, sdo4 is used to transmit data from the tx4 serial transmit shift register. sdi1 input serial data input 1 ?when programmed as a receiver, sdi1 is used to receive serial data into the rx1 serial receive shift register. pc7 input, output, or disconnected port c 7 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo3/ sdo3_1 output gpio disconnected serial data output 3 ?when programmed as a tran smitter, sdo3 is used to transmit data from the tx3 serial transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 3. sdi2/ sdi2_1 input serial data input 2 ?when programmed as a receiver, sdi2 is used to receive serial data into the rx2 serial receive shift register. when enabled for esai_1 operation, this is the esai_1 serial data input 2. pc8/pe8 input, output, or disconnected port c 8 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. when enabled for esai_1 gpio, this is the port e 8 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. table 1-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
1-20 DSP56366 advance information motorola signal/connection descriptions enhanced serial audio interface sdo2/ sdo2_1 output gpio disconnected serial data output 2 ?when programmed as a tran smitter, sdo2 is used to transmit data from the tx2 serial transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 2. sdi3/ sdi3_1 input serial data input 3 ?when programmed as a rece iver, sdi3 is used to receive serial data into the rx3 serial receive shift register. when enabled for esai_1 operation, this is the esai_1 serial data input 3. pc9/pe9 input, output, or disconnected port c 9 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. when enabled for esai_1 gpio, this is the port e 9 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo1/ sdo1_1 output gpio disconnected serial data output 1 ?sdo1 is used to transmit data from the tx1 serial transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 1. pc10/ pe10 input, output, or disconnected port c 10 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. when enabled for esai_1 gpio, this is the port e 10 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo0/ sdo0_1 output gpio disconnected serial data output 0 ?sdo0 is used to transmit data from the tx0 serial transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 0. pc11/ pe11 input, output, or disconnected port c 11 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. when enabled for esai_1 gpio, this is the port e 11 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. table 1-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
signal/connection descriptions enhanced serial audio interface_1 motorola DSP56366 advance information 1-21 enhanced serial a udio interface_1 table 1-12 enhanced seri al audio interface_1 signals signal name signal type state during reset signal description fsr_1 input or output gpio disconnected frame sync for receiver_1 ?this is the receiver frame sync input/output signal. in the asynchronous mode (syn= 0), the fsr pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmitter exte rnal buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direc tion is determined by the rfsd bit in the rccr register. wh en configured as the output flag of1, this pin will reflect the value of the of1 bit in the saicr register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pe1 input, output, or disconnected port e 1 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input cannot tolerate 5 v. fst_1 input or output gpio disconnected frame sync for transmitter_1 ?this is the transmit ter frame sync input/ output signal. for synchronous mode, th is signal is the frame sync for both transmitters and receivers. for async hronous mode, fst is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direction (tfsd) bit in the esai transmit clock control register (tccr). pe4 input, output, or disconnected port e 4 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input cannot tolerate 5 v.
1-22 DSP56366 advance information motorola signal/connection descriptions enhanced serial audio interface_1 sckr_1 input or output gpio disconnected receiver serial clock_1 ?sckr provides the receiver serial bit clock for the esai. the sckr operates as a clock input or output used by all the enabled receivers in the asynchronous m ode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direc tion is determined by the rckd bit in the rccr register. when configured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pe0 input, output, or disconnected port e 0 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. the default state after re set is gpio disconnected. this input cannot tolerate 5 v. sckt_1 input or output gpio disconnected transmitter serial clock_1 ?this signal provides the serial bit rate clock for the esai. sckt is a clock input or output used by all enabled transmitters and receivers in sync hronous mode, or by all enabled transmitters in asynchronous mode. pe3 input, output, or disconnected port e 3 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. the default state after re set is gpio disconnected. this input cannot tolerate 5 v. sdo5_1 output gpio disconnected serial data output 5_1 ?when programmed as a tr ansmitter, sdo5 is used to transmit data from the tx5 serial transmit shift register. sdi0_1 input serial data input 0_1 ?when programmed as a receiver, sdi0 is used to receive serial data into the rx0 serial receive shift register. pe6 input, output, or disconnected port e 6 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or interna lly disconnected. the default state after re set is gpio disconnected. this input cannot tolerate 5 v. table 1-12 enhanced serial audio interface_1 signals signal name signal type state during reset signal description
signal/connection descriptions spdif transmitter digi tal audio interface motorola DSP56366 advance information 1-23 spdif transmitter digi tal audio interface sdo4_1 output gpio disconnected serial data output 4_1 ?when programmed as a transmitter, sdo4 is used to transmit data from the tx4 serial transmit shift register. sdi1_1 input serial data input 1_1 ?when programmed as a rece iver, sdi1 is used to receive serial data into the rx1 serial receive shift register. pe7 input, output, or disconnected port e 7 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. table 1-13 digital audio interface (dax) signals signal name type state during reset signal description aci input gpio disconnected audio clock input ?this is the dax clock input. when programmed to use an external clock, this input su pplies the dax clock. the external clock frequency must be 256, 384, or 512 ti mes the audio sampling frequency (256 fs, 384 fs or 512 fs, respectively). pd0 input, output, or disconnected port d 0 ?when the dax is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. ado output gpio disconnected digital audio data output ?this signal is an audio and non-audio output in the form of aes/ebu, cp340 and iec9 58 data in a biphase mark format. pd1 input, output, or disconnected port d 1 ?when the dax is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. table 1-12 enhanced seri al audio interface_1 signals signal name signal type state during reset signal description
1-24 DSP56366 advance information motorola signal/connection descriptions timer timer jtag/once interface table 1-14 timer signal signal name type state during reset signal description tio0 input or output input timer 0 schmitt-trigger input/output ?when timer 0 functions as an external event counter or in measur ement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer i nput/output through the timer 0 control/status register (tcsr0). if tio0 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leav e it defined as gpio input but connected to vcc through a pull-up resist or in order to ensure a stable logic level at this input. this input is 5 v tolerant. table 1-15 jtag/once interface signal name signal type state during reset signal description tck input input test clock ?tck is a test clock input signal used to synchronize the jtag test logic. it has an internal pull-up resistor. this input is 5 v tolerant. tdi input input test data input ?tdi is a test data serial input si gnal used for test instructions and data. tdi is sampled on the rising edge of tck and has an inte rnal pull-up resistor. this input is 5 v tolerant. tdo output tri-stated test data output ?tdo is a test data serial output si gnal used for test instructions and data. tdo is tri-statable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on th e falling edge of tck. tms input input test mode select ?tms is an input signal used to sequence the test controller?s state machine. tms is sampled on the rising edge of tck and has an internal pull-up resistor. this input is 5 v tolerant.
signal/connection descriptions motorola DSP56366 advance information 1-25
1-26 DSP56366 advance information motorola signal/connection descriptions
motorola DSP56366 advance information 2-1 section 2 specifications introduction the DSP56366 is a high density cmos device with transistor-transistor logic (ttl) compatible inputs and outputs. the DSP56366 specifica tions are preliminary and are from design simulations, and may not be fully tested or guaranteed. fina lized specifications will be publis hed after full characterization and device qualifications are complete. maximum ratings note: in the calculation of timing requiremen ts, adding a maximum value of one specification to a minimum value of anothe r specification does not yield a reasonable sum. a maximum specification is calculate d using a worst case variation of process parameter values in one direction. the mi nimum specification is calculated using the worst case for the same parameters in the op posite direction. therefore, a ?maximum? value for a specification w ill never occur in the same de vice that has a ?minimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. caution this device contains circ uitry protecting against damage due to high static voltage or electrical fields. however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either gnd or v cc ). the suggested value for a pullup or pulldown resistor is 10 k ? .
2-2 DSP56366 advance information motorola specifications thermal characteristics thermal characteristics table 2-1 maximum ratings rating 1 symbol value 1, 2 unit supply voltage v cc ? 0.3 to +4.0 v all input voltages excludi ng ?5 v tolerant? inputs 3 v in gnd -0.3 to v cc + 0.3 v all ?5 v tolerant? input voltages 3 v in5 gnd ? 0.3 to v cc + 3.95 v current drain per pin excluding v cc and gnd i10ma operating temperature range t j ta ? 40 to +105 ? 40 to +85 c storage temperature t stg ? 55 to +125 c notes: 1. gnd = 0 v, v cc = 3.3 v 0.16 v, t j = ?40 c to +105 c, cl = 50 pf 2. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reliability or caus e permanent damage to the device. 3. caution : all ?5 v tolerant? input voltages must not be more than 3.95 v grea ter than the supply voltage; this restriction applies to ?power on?, as well as during normal ope ration. in any case, the input voltages cannot be more than 5.75 v. ?5 v tolerant? inputs are inputs that tolerate 5 v. table 2-2 thermal characteristics characteristic symbol tqfp value unit junction-to-ambient thermal resistance 1, 2 natural convection r ja or ja 37 c/w junction-to-case th ermal resistance 3 r jc or jc 7 c/w thermal characterization parameter 4 natural convection jt 2.0 c/w notes: 1. junction temperature is a functi on of die size, on-chip power dissipati on, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow , power dissipation of othe r components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 wi th the single layer board horizontal. 3. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec- 883 method 1012.1). 4. thermal characterization parameter indicating the temperatur e difference between pack age top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt.
specifications dc electrical characteristics motorola DSP56366 advance information 2-3 dc electrical characteristics table 2-3 dc electrical characteristics 6 characteristics symbol min typ max unit supply voltage v cc 3.14 3.3 3.46 v input high voltage ?d(0:23), bg , bb , t a , esai_1 (except sdo4_1) v ih 2.0 ? v cc v ?mod 1 /irq 1 , reset , pinit/nmi and all jtag/esai/tim er/hdi08/dax/ esai_1 (only sdo4_1) /shi (spi mode) v ihp 2.0 ? v cc + 3.95 ?shi (i2c mode) v ihp 1.5 ? v cc + 3.95 ? extal 8 v ihx 0.8 v cc ?v cc input low voltage ?d(0:23), bg , bb , t a , esai_1 (except sdo4_1) v il ?0.3 ? 0.8 v ?mod 1 /irq 1 , reset , pinit/nmi and all jtag/esai/tim er/hdi08/dax/ esai_1 (only sdo4_1) /shi (spi mode) v ilp ?0.3 ? 0.8 ?shi (i2c mode) v ilp ?0.3 ? 0.3 x v cc ? extal 8 v ilx ?0.3 ? 0.2 x v cc input leakage current i in ?10 ? 10 a high impedance (off-state) input current (@ 2.4 v / 0.4 v) i tsi ?10 ? 10 a output high voltage ?ttl (i oh = ?0.4 ma) 5,7 v oh 2.4 ? ? v ?cmos (i oh = ?10 a) 5 v cc ? 0.01 ? ? v output low voltage ?ttl (i ol = 3.0 ma, open-drain pins i ol = 6.7 ma) 5,7 v ol ?? 0.4 v ?cmos (i ol = 10 a) 5 ? ? 0.01 internal supply current 2 at internal clock of 120mhz ?in normal mode i cci ? 116 200 ma ? in wait mode i ccw ?7.3 25ma ? in stop mode 4 i ccs ?1 10ma pll supply current ?1 2.5ma input capacitance 5 c in ? ? 10 pf
2-4 DSP56366 advance information motorola specifications dc electrical characteristics notes: 1. refers to moda/irqa , modb/irqb , modc/irqc ,and modd/irqd pins 2. power consumption considerations on page 4-4 provides a formula to compute the estimated current requirements in normal mode. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). measurements are ba sed on synthetic intensive d sp benchmarks. the power cons umption numbers in this specification are 90% of the measured results of this benchmark. this reflects typical dsp applicati ons. typical internal supply current is measured with v cc = 3.3 v at t j = 105c. maximum internal supply current is measured with v cc = 3.46 v at t j = 105c. 3. deleted. 4. in order to obtain these results, all inputs, which are not disconnected at stop mode, must be terminated (i.e., not allowed to float). 5. periodically sampled and not 100% tested 6. v cc = 3.3 v .16 v; t j = ? 40c to +105c, c l = 50 pf 7. this characteristic does not apply to pcap. 8. driving extal to the low v ihx or the high v ilx value may cause additional pow er consumption (dc current). to minimize power consumption, the minimum v ihx should be no lower than 0.9 v cc and the maximum v ilx should be no higher than 0.1 v cc . table 2-3 dc electrical characteristics 6 (continued) characteristics symbol min typ max unit
specifications ac electrical characteristics motorola DSP56366 advance information 2-5 ac electrical characteristics the timing waveforms shown in the ac electrica l characteristics section are tested with a v il maximum of 0.3 v and a v ih minimum of 2.4 v for all pins except exta l, which is tested using the input levels shown in note 8 of the previous table. ac timing specificatio ns, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal?s transition. DSP56366 output levels are measured with the production test machine v ol and v oh reference levels set at 0.4 v and 2.4 v, respectively. note: although the minimum value for the frequency of extal is 0 mhz, the device ac test conditions are 15 mhz and rated speed.
2-6 DSP56366 advance information motorola specifications internal clocks internal clocks table 2-4 internal clocks characteristics symbol expression 1, 2 min typ max internal operation frequency with pll enabled f? (ef mf)/ (pdf df) ? internal operation frequency with pll disabled f? ef/2 ? internal clock high period t h ? with pll disabled ? et c ? ? with pll enabled and mf 4 0.49 et c pdf df/mf ? 0.51 et c pdf df/mf ? with pll enabled and mf > 4 0.47 et c pdf df/mf ? 0.53 et c pdf df/mf internal clock low period t l ? with pll disabled ? et c ? ? with pll enabled and mf 4 0.49 et c pdf df/mf ? 0.51 et c pdf df/mf ? with pll enabled and mf > 4 0.47 et c pdf df/mf ? 0.53 et c pdf df/mf internal clock cycle time with pll enabled t c ? et c pdf df/mf ? internal clock cycle time with pll disabled t c ?2 et c ? instruction cycle time i cyc ?t c ? notes: 1. df = division factor ef = external frequency et c = external clock cycle mf = multiplication factor pdf = predivision factor t c = internal clock cycle 2. see the pll and clock generation section in the dsp56300 family manual for a detailed discussion of the pll.
specifications external clock operation motorola DSP56366 advance information 2-7 external clock operation the DSP56366 system clock is an externally s upplied square wave voltage source connected to extal( figure 2-1 ). figure 2-1 e xternal clock timing table 2-5 clock operation no. characteristics symbol min max 1 frequency of extal (e xtal pin frequency) the rise and fall time of this external clock should be 3 ns maximum. ef 0 120.0 2 extal input high 1, 2 ? with pll disabled (46.7%?53.3% duty cycle 6 ) et h 3.89 ns ? with pll enabled (42.5%?57.5% duty cycle 6 ) 3.54 ns 157.0 s 3 extal input low 1, 2 ? with pll disabled (46.7%?53.3% duty cycle 6 ) et l 3.89 ns ? with pll enabled (42.5%?57.5% duty cycle 6 ) 3.54 ns 157.0 s 4 extal cycle time 2 ? with pll disabled et c 8.33 ns ? with pll enabled 8.33 ns 273.1 s 7 instruction cycle time = i cyc = t c 4 ? with pll disabled i cyc 16.66 ns ? with pll enabled 8.33 ns 8.53 s notes: 1. measured at 50% of the input transition 2. the maximum value for pll en abled is given for minimum v co and maximum mf. 3. 4. the maximum value for pll enabled is given for minimum vco and maximum df. 5. 6. the indicated duty cycle is for the specified maximum frequency for which a part is rated. the minimum clock high or low time required for correct operation, however, remains the same at lower operating frequenc ies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specifie d duty cycle as long as the minimum high time and low time requirements are met. extal v il v ihc midpoint note: the midpoint is 0.5 (v ihc + v ilc ). et h et l et c 3 4 2
2-8 DSP56366 advance information motorola specifications phase lock loop (pll) characteristics phase lock loop (p ll) characteristics table 2-6 pll characteristics characteristics min max unit v co frequency when pll enabled (mf e f 2/pdf) 30 240 mhz pll external capacitor (pcap pin to v ccp ) (c pcap 1) pf ?@ mf 4 (mf 580) ? 100 (mf 780) ? 140 ?@ mf > 4 mf 830 mf 1470 notes: 1. c pcap is the value of the pll capacitor (c onnected between the pcap pin and v ccp ). the recommended value in pf for c pcap can be computed from one of the following equations: (mf x 680)-120 , for mf 4, or mf x 1100 , for mf > 4.
specifications reset, stop, mode select, and interrupt timing motorola DSP56366 advance information 2-9 reset, stop, mo de select, and interrupt timing table 2-7 reset, stop, mode select, and interrupt timing 6 no. characteristics expression min max unit 8 delay from reset assertion to all pi ns at reset value 3 ? ? 26.0 ns 9 required reset duration 4 ? power on, external clock generator, pll disabled 50 et c 416.7 ? ns ? power on, external cloc k generator, pll enabled 1000 et c 8.3 ? s ? during normal operation 2.5 t c 20.8 ? ns 10 delay from asynchronous reset deassertion to first external address output (i nternal reset deassertion) 5 ?minimum 3.25 t c + 2.0 29.1 ? ns ? maximum 20.25 t c + 7.50 ? 176.2 ns 13 mode select setup time 30.0 ? ns 14 mode select hold time 0.0 ? ns 15 minimum edge-triggered interr upt request assertion width 5.5 ? ns 16 minimum edge-triggered interrupt request deassertion width 5.5 ? ns 17 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory access address out valid ? caused by first interrupt instruction fetch 4.25 t c + 2.0 37.4 ? ns ? caused by first interrupt instruction execution 7.25 t c + 2.0 62.4 ? ns 18 delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer out put valid caused by first interrupt instruction execution 10 t c + 5.0 88.3 ? ns 19 delay from address output vali d caused by first interrupt instruction execute to interr upt request deassertion for level sensitive fast interrupts 1 3.75 t c + ws t c ? 10.94 ? note 7 ns 20 delay from rd assertion to interrupt request deassertion for level sensitive fast interrupts 1 3.25 t c + ws t c ? 10.94 ? note 7 ns 21 delay from wr assertion to interrupt request deassertion for level sensitive fast interrupts 1 ns ? dram for all ws (ws + 3.5) t c ? 10.94 ? note 7 ?sram ws = 1 (ws + 3.5) t c ? 10.94 ? note 7 ? sram ws = 2, 3 (ws + 3) t c ? 10.94 ? note 7 ?sram ws 4 (ws + 2.5) t c ? 10.94 ? note 7 24 duration for irqa assertion to recover from stop state 4.9 ?
2-10 DSP56366 advance information motorola specifications reset, stop, mode select, and interrupt timing 25 delay from irqa assertion to fetch of first instruction (when exiting stop) 2, 3 ? pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (omr bit 6 = 0) plc et c pdf + (128 k ? plc/2) t c ??ms ? pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (omr bit 6 = 1) plc et c pdf + (23.75 0.5) t c ??ms ? pll is active during stop (pctl bit 17 = 1) (implies no stop delay) (8.25 0.5) t c 64.6 72.9 ns 26 duration of level sensitive irqa assertion to ensure interrupt service (w hen exiting stop) 2, 3 ? pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (omr bit 6 = 0) plc et c pdf + (128k ? plc/2) t c ??ms ? pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (omr bit 6 = 1) plc et c pdf + (20.5 0.5) t c ??ms ? pll is active during stop (pctl bit 17 = 1) (implies no stop delay) 5.5 t c 45.8 ? ns 27 interrupt requests rate ? hdi08, esai, esai_1 , shi, dax, timer 12t c ? 100.0 ns ?dma 8t c ? 66.7 ns ?irq , nmi (edge trigger) 8t c ? 66.7 ns ?irq (level trigger) 12t c ? 100.0 ns 28 dma requests rate ? data read from hdi08, esai, esai_1, shi, dax 6t c ? 50.0 ns ? data write to hdi08, esai, esai_1, shi, dax 7t c ? 58.0 ns ?timer 2t c 16.7 ?irq , nmi (edge trigger) 3t c ? 25.0 ns table 2-7 reset, stop, mode select, and interrupt timing 6 (continued) no. characteristics expression min max unit
specifications reset, stop, mode select, and interrupt timing motorola DSP56366 advance information 2-11 figure 2-2 reset timing 29 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory (dma source ) access address out valid 4.25 t c + 2.0 37.4 ? ns notes: 1. when using fast interrupts and irqa , irqb , irqc , and irqd are defined as level-sens itive, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing restri ctions, the deassert ed edge-triggered mode is recommended when using fast interrupts. long interrupts are reco mmended when using level-sensitive mode. 2. this timing depends on several settings: for pll disable, using extern al clock (pctl bit 16 = 1), no stabilization delay is required and recovery time will be defined by the pctl bi t 17 and omr bit 6 settings. for pll enable, if pctl bit 17 is 0, the pll is shut down during stop. recovering fro m stop requires the pll to get locked. the pll lock procedure duration, pll lock cy cles (plc), may be in the range of 0 to 1000 cycles. this procedure occurs in parallel with the stop delay coun ter, and stop recovery will end when the last of these two events occurs: the stop delay counter comple tes count or pll lock procedure completion. plc value for pll disable is 0. the maximum value for et c is 4096 (maximum mf) divided by the desi red internal frequency (i.e., for 120 mhz it is 4096/120 mhz = 34.1 s). during the stabilization period, t c , t h, and t l will not be constant, and their width may vary, so timing may vary as well. 3. periodically sample d and not 100% tested 4. r eset duration is measured duri ng the time in which reset is asserted, v cc is valid, and the extal input is active and valid. when the v cc is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circ uitry will be in an uniniti alized state that can re sult in significant power consumption and heat-up. designs should minimize this state to the shortest possible duration. 5. if pll does not lose lock 6. v cc = 3.3 v 0.16 v; t j = ?40c to + 105c, c l = 50 pf 7. ws = number of wait states (measu red in clock cycles, number of t c ). use expression to compute maximum value. table 2-7 reset, stop, mode select, and interrupt timing 6 (continued) no. characteristics expression min max unit v ih reset reset value first fetch all pins a0?a17 8 9 10 aa0460
2-12 DSP56366 advance information motorola specifications reset, stop, mode select, and interrupt timing figure 2-3 external fast interrupt timing figure 2-4 external interrupt timing (negative edge-triggered) a0?a17 rd a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi b) general purpose i/o i rqa , irqb , irqc , i rqd , nmi wr 20 21 19 17 18 first interrupt instruction execution/fetch irqa , irqb , irqc, i rqd , nmi irqa , irqb , i rqc, irqd , nmi 15 16 aa0463
specifications reset, stop, mode select, and interrupt timing motorola DSP56366 advance information 2-13 figure 2-5 operating mode select timing figure 2-6 recovery from stop state using irqa figure 2-7 recovery from stop state using irqa interrupt service reset moda, modb, modc, modd, pinit v ih irqa , irqb , i rqd , nmi v ih v il v ih v il 13 14 aa0465 first instruction fetch irqa a0?a17 24 25 aa0466 irqa a0?a17 first irqa interrupt instruction fetch 26 25 aa0467
2-14 DSP56366 advance information motorola specifications reset, stop, mode select, and interrupt timing figure 2-8 external memory access (dma source) timing 29 dma source address first interrupt instruction execution a0?a17 rd wr irqa , irqb , irqc, i rqd , nmi aa1104
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-15 external memory expansion port (port a) sram timing table 2-8 sram read and write accesses 3 no. characteristics symbol expression 1 min max unit 100 address valid and aa assertion pulse width t rc , t wc (ws + 1) t c ? 4.0 [1 ws 3] 12.0 ? ns (ws + 2) t c ? 4.0 [4 ws 7] 46.0 ? ns (ws + 3) t c ? 4.0 [ws 8] 87.0 ? ns 101 address and aa valid to wr assertion t as 0.25 t c ? 2.0 [ws = 1] 0.1 ? ns 1.25 t c ? 2.0 [ws 4] 8.4 ? ns 102 wr assertion pulse width t wp 1.5 t c ? 4.0 [ws = 1] 8.5 ? ns all frequencies: ws t c ? 4.0 [2 ws 3] 12.7 ? ns (ws ? 0.5) t c ? 4.0 [ws 4] 25.2 ? ns 103 wr deassertion to address not valid t wr 0.25 t c ? 2.0 [1 ws 3] 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 8.4 ? ns 2.25 t c ? 2.0 [ws 8] 16.7 ? ns all frequencies: 1.25 t c ? 4.0 [4 ws 7] 6.4 ? ns 2.25 t c ? 4.0 [ws 8] 14.7 ? ns 104 address and aa valid to input data valid t aa , t ac (ws + 0.75) t c ? 7.0 [ws 1] ?7.6ns 105 rd assertion to input data valid t oe (ws + 0.25) t c ? 7.0 [ws 1] ?3.4ns 106 rd deassertion to data not valid (data hold time) t ohz 0.0 ? ns 107 address valid to wr deassertion 2 t aw (ws + 0.75) t c ? 4.0 [ws 1] 10.6 ? ns 108 data valid to wr deassertion (data setup time) t ds (t dw ) (ws ? 0.25) t c ? 3.0 [ws 1] 3.2 ? ns
2-16 DSP56366 advance information motorola specifications external memory expansion port (port a) 109 data hold time from wr deassertion t dh 0.25 t c ? 2.0 [1 ws 3] 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 8.4 ? ns 2.25 t c ? 2.0 [ws 8] 16.7 ? ns 110 wr assertion to data active ? 0.75 t c ? 3.7 [ws = 1] 2.5 ? ns 0.25 t c ? 3.7 [2 ws 3] 0.0 ? ? 0.25 t c ? 3.7 [ws 4] 0.0 ? 111 wr deassertion to data high impedance ? 0.25 t c + 0.2 [1 ws 3] ?2.3 ns 1.25 t c + 0.2 [4 ws 7] ? 10.6 2.25 t c + 0.2 [ws 8] ? 18.9 112 previous rd deassertion to data active (write) ? 1.25 t c ? 4.0 [1 ws 3] 6.4 ? ns 2.25 t c ? 4.0 [4 ws 7] 14.7 ? 3.25 t c ? 4.0 [ws 8] 23.1 ? 113 rd deassertion time 0.75 t c ? 4.0 [1 ws 3] 2.2 ? ns 1.75 t c ? 4.0 [4 ws 7] 10.6 ? ns 2.75 t c ? 4.0 [ws 8] 18.9 ? ns 114 wr deassertion time 0.5 t c ? 4.0 [ws = 1] 0.2 ? ns t c ? 2.0 [2 ws 3] 6.3 ? ns 2.5 t c ? 4.0 [4 ws 7] 16.8 ? ns 3.5 t c ? 4.0 [ws 8] 25.2 ? ns 115 address valid to rd assertion 0.5 t c ? 4.0 0.2 ? ns 116 rd assertion pulse width (ws + 0.25) t c ? 4.0 6.4 ? ns 117 rd deassertion to address not valid 0.25 t c ? 2 .0 [1 ws 3] 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 8.4 ? ns 2.25 t c ? 2.0 [ws 8] 16.7 ? ns table 2-8 sram read and write accesses 3 (continued) no. characteristics symbol expression 1 min max unit
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-17 figure 2-9 sram read access 118 ta setup before rd or wr deassertion 4 0.25 t c + 2.0 4.1 ? ns 119 ta hold after rd or wr deassertion 0.0 ? ns notes: 1. ws is the number of wait states specified in the bcr. 2. timings 100, 107 are guarant eed by design, not tested. 3. all timings for 100 mhz are measured from 0.5 vcc to .05 vcc 4. in the case of ta negation: timing 118 is relative to the deassertion edge of rd or wr were ta to remain active table 2-8 sram read and write accesses 3 (continued) no. characteristics symbol expression 1 min max unit a0?a17 rd wr d0?d23 aa0?aa2 115 105 106 113 104 116 117 100 aa0468 ta 119 data in 118
2-18 DSP56366 advance information motorola specifications external memory expansion port (port a) figure 2-10 sram write access a0?a17 wr rd data out d0?d23 aa0?aa2 100 102 101 107 114 108 109 103 ta 119 118
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-19 dram timing the selection guides provided in figure 2-11 and figure 2-14 should be used for primary selection only. final selection should be based on the timing provided in the followi ng tables. as an example, the selection guide suggests that 4 wait states must be used for 100 mhz operation when using page mode dram. however, by using the inform ation in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determ ining which timing prevents operation at 100 mhz, running the chip at a slightly lowe r frequency (e.g., 95 mhz), using faster dram (if it becomes available), and control factors such as capacitive an d resistive load to improve overall sys tem performance. figure 2-11 dram page mode wait states selection guide chip frequency (mhz) dram type (t rac ns) 100 80 70 60 40 66 80 100 1 wait states 2 wait states 3 wait states 4 wait states note: this figure should be use for primary selection. for exact and detailed timings see the following tables. aa04 7 50 120
2-20 DSP56366 advance information motorola specifications external memory expansion port (port a) table 2-9 dram page mode timings, one wait state (low-power applications) 1, 2, 3 no. characteristics symbol expression 20 mhz 6 30 mhz 6 unit min max min max 131 page mode cycle time for two consecutive accesses of the same direction t pc 2 t c 100.0 ? 66.7 ? ns page mode cycle time for mixed (read and write) accesses 1.25 t c 62.5 ? 41.7 ? 132 cas assertion to da ta valid (read) t cac t c ? 7.5 ? 42.5 ? 25.8 ns 133 column address valid to data valid (read) t aa 1.5 t c ? 7.5 ? 67.5 ? 42.5 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 2 t c ? 4.0 96.0 ? 62.7 ? ns 137 cas assertion pulse width t cas 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 138 last cas deassertion to ras deassertion 4 ? brw[1:0] = 00 t crp 1.75 t c ? 6.0 81.5 ? 52.3 ? ns ? brw[1:0] = 01 3.25 t c ? 6.0 156.5 102.2 ? ns ? brw[1:0] = 10 4.25 t c ? 6.0 206.5 135.5 ? ns ? brw[1:0] = 11 6.25 t c ? 6.0 306.5 ? 202.1 ? ns 139 cas deassertion pulse width t cp 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 140 column address valid to cas assertion t asc 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 141 cas assertion to column address not valid t cah 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 142 last column address valid to ras deassertion t ral 2 t c ? 4.0 96.0 ? 62.7 ? ns 143 wr deassertion to cas assertion t rcs 0.75 t c ? 3.8 33.7 ? 21.2 ? ns 144 cas deassertion to wr assertion t rch 0.25 t c ? 3.7 8.8 ? 4.6 ? ns 145 cas assertion to wr deassertion t wch 0.5 t c ? 4.2 20.8 ? 12.5 ? ns 146 wr assertion pulse widt h t wp 1.5 t c ? 4.5 70.5 ? 45.5 ? ns 147 last wr assertion to ras deassertion t rwl 1.75 t c ? 4.3 83.2 ? 54.0 ? ns 148 wr assertion to cas deassertion t cwl 1.75 t c ? 4.3 83.2 ? 54.0 ? ns 149 data valid to cas assertion (write) t ds 0.25 t c ? 4.0 8.5 ? 4.3 ? ns 150 cas assertion to data not valid (write) t dh 0.75 t c ? 4.0 33.5 ? 21.0 ? ns
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-21 151 wr assertion to cas assertion t wcs t c ? 4.3 45.7 ? 29.0 ? ns 152 last rd assertion to ras deassertion t roh 1.5 t c ? 4.0 71.0 ? 46.0 ? ns 153 rd assertion to data valid t ga t c ? 7.5 ? 42.5 ? 25.8 ns 154 rd deassertion to data not valid 5 t gz 0.0 ? 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 37.2 ? 24.7 ? ns 156 wr deassertion to data high impedance 0.25 t c ? 12.5 ? 8.3 ns notes: 1. the number of wait states for page mode access is specified in the dcr. 2. the refresh period is specified in the dcr. 3. all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 2 t c for read-after-read or wr ite-after-write sequences). 4. brw[1:0] (dram control register bits) defines the number of wait states th at should be inserted in each dram out-of-page access. 5. rd deassertion will al ways occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 6. reduced dsp clock speed allo ws use of page mode dram with one wait state (see figure 2-14 .). table 2-10 dram page mode timings, two wait states 1, 2, 3, 7 no. characteristics symbol expression 66 mhz 80 mhz unit min max min max 131 page mode cycl e time for two consecutive accesses of the same direction t pc 2 t c 45.4 ? 37.5 ? ns page mode cycl e time for mixed (read and write) accesses 1.25 t c 41.1 ? 34.4 ? 132 cas assertion to data valid (read) t cac 1.5 t c ? 7.5 ? 15.2 ? ? ns 1.5 t c ? 6.5 ? ? ? 12.3 ns 133 column address valid to data valid (read) t aa 2.5 t c ? 7.5 ? 30.4 ? ? ns 2.5 t c ? 6.5 ? ? ? 24.8 ns 134 cas deassertion to data not valid (read hold time) t off 0.0?0.0? ns 135 last cas assertion to ras deassertion t rsh 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 136 previous cas deassertion to ras deassertion t rhcp 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 137 cas assertion pulse width t cas 1.5 t c ? 4.0 18.7 ? 14.8 ? ns table 2-9 dram page mode timings, one wait state (low-power applications) 1, 2, 3 (continued) no. characteristics symbol expression 20 mhz 6 30 mhz 6 unit min max min max
2-22 DSP56366 advance information motorola specifications external memory expansion port (port a) 138 last cas deassertion to ras deassertion 5 ? brw[1:0] = 00 t crp 2.0 t c ? 6.0 24.4 ? 19.0 ? ns ? brw[1:0] = 01 3.5 t c ? 6.0 47.2 ? 37.8 ? ns ? brw[1:0] = 10 4.5 t c ? 6.0 62.4 ? 50.3 ? ns ? brw[1:0] = 11 6.5 t c ? 6.0 92.8 ? 75.3 ? ns 139 cas deassertion pulse width t cp 1.25 t c ? 4.0 14.9 ? 11.6 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 11.2 ? 8.5 ? ns 141 cas assertion to column address not valid t cah 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 142 last column address valid to ras deassertion t ral 3 t c ? 4.0 41.5 ? 33.5 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 3.8 15.1 ? 11.8 ? ns 144 cas deassertion to wr assertion t rch 0.5 t c ? 3.7 3.9?2.6? ns 145 cas assertion to wr deassertion t wch 1.5 t c ? 4.2 18.5 ? 14.6 ? ns 146 wr assertion pulse width t wp 2.5 t c ? 4.5 33.5 ? 26.8 ? ns 147 last wr assertion to ras deassertion t rwl 2.75 t c ? 4.3 33.4 ? 26.8 ? ns 148 wr assertion to cas deassertion t cwl 2.5 t c ? 4.3 33.6 ? 27.0 ? ns 149 data valid to cas assertion (write) t ds 0.25 t c ? 3.7 0.1 ? ? ? ns 0.25 t c ? 3.0 ? ? 0.1 ? ns 150 cas assertion to data not valid (write) t dh 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 151 wr assertion to cas assertion t wcs t c ? 4.3 10.9 ? 8.2 ? ns 152 last rd assertion to ras deassertion t roh 2.5 t c ? 4.0 33.9 ? 27.3 ? ns 153 rd assertion to data valid t ga 1.75 t c ? 7.5 ? 19.0 ? ? ns 1.75 t c ? 6.5 ? ? ? 15.4 ns 154 rd deassertion to data not valid 6 t gz 0.0?0.0? ns 155 wr assertion to data active 0.75 t c ? 0.3 11.1 ? 9.1 ? ns 156 wr deassertion to data high impedance 0.25 t c ?3.8?3.1ns table 2-10 dram page mode timings, two wait states 1, 2, 3, 7 (continued) no. characteristics symbol expression 66 mhz 80 mhz unit min max min max
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-23 notes: 1. the number of wait states for pa ge mode access is sp ecified in the dcr. 2. the refresh period is specified in the dcr. 3. the asynchronous delays specified in the expressions are valid for DSP56366. 4. all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 3 t c for read-after-read or wr ite-after-write sequences). 5. brw[1:0] (dram control register bits) defines the number of wait states that should be inserted in each dram out-of-page access. 6. rd deassertion will al ways occur after cas deassertion; therefore, the restricted timing is t off and not t gz. 7. there are no drams fast enough to fit to two wait states page mode @ 100mhz (see figure 2-11 ) table 2-11 dram page mode timings, three wait states 1, 2, 3 no. characteristics symbol expression min max unit 131 page mode cycle time for two consecutive ac cesses of the same direction t pc 2 t c 40.0 ? ns page mode cycle time for mi xed (read and write) accesses 1.25 t c 35.0 ? 132 cas assertion to data valid (read) t cac 2 t c ? 7.0 ? 13.0 ns 133 column address valid to data valid (read) t aa 3 t c ? 7.0 ? 23.0 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 2.5 t c ? 4.0 21.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 4.5 t c ? 4.0 41.0 ? ns 137 cas assertion pulse width t cas 2 t c ? 4.0 16.0 ? ns 138 last cas deassertion to ras assertion 5 ?brw[1:0] = 00 t crp 2.25 t c ? 6.0 ? ? ns ? brw[1:0] = 01 3.75 t c ? 6.0 ? ? ns ? brw[1:0] = 10 4.75 t c ? 6.0 41.5 ? ns ? brw[1:0] = 11 6.75 t c ? 6.0 61.5 ? ns 139 cas deassertion pulse width t cp 1.5 t c ? 4.0 11.0 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 6.0 ? ns 141 cas assertion to column address not valid t cah 2.5 t c ? 4.0 21.0 ? ns 142 last column address valid to ras deassertion t ral 4 t c ? 4.0 36.0 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 4.0 8.5 ? ns 144 cas deassertion to wr assertion t rch 0.75 t c ? 4.0 3.5 ? ns 145 cas assertion to wr deassertion t wch 2.25 t c ? 4.2 18.3 ? ns 146 wr assertion pulse width t wp 3.5 t c ? 4.5 30.5 ? ns 147 last wr assertion to ras deassertion t rwl 3.75 t c ? 4.3 33.2 ? ns 148 wr assertion to cas deassertion t cwl 3.25 t c ? 4.3 28.2 ? ns 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.0 1.0 ? ns table 2-10 dram page mode timings, two wait states 1, 2, 3, 7 (continued) no. characteristics symbol expression 66 mhz 80 mhz unit min max min max
2-24 DSP56366 advance information motorola specifications external memory expansion port (port a) 150 cas assertion to data not valid (write) t dh 2.5 t c ? 4.0 21.0 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 8.2 ? ns 152 last rd assertion to ras deassertion t roh 3.5 t c ? 4.0 31.0 ? ns 153 rd assertion to data valid t ga 2.5 t c ? 7.0 ? 18.0 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 7.2 ? ns 156 wr deassertion to da ta high impedance 0.25 t c ?2.5 ns notes: 1. the number of wait states for page mode access is specified in the dcr. 2. the refresh period is specified in the dcr. 3. the asynchronous delays specified in the expressions are valid for DSP56366 . 4. all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 4 t c for read-after-read or wr ite-after-write sequences). 5. brw[1:0] (dram control regi ster bits) defines the numbe r of wait states that shoul d be inserted in each dram out-of page-access. 6. rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 2-11 dram page mode timings, three wait states 1, 2, 3 (continued) no. characteristics symbol expression min max unit
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-25 table 2-12 dram page mode timings, four wait states 1, 2, 3 no. characteristics symbol expression min max 131 page mode cycle time for two consecutive accesses of the same direction. t pc 5 t c 41.7 ? ns page mode cycle time for mi xed (read and write) accesses 4.5 t c 37.5 ? 132 cas assertion to da ta valid (read) t cac 2.75 t c ? 7.0 ? 15.9 ns 133 column address valid to data valid (read) t aa 3.75 t c ? 7.0 ? 24.2 ns 134 cas deassertion to data no t valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 3.5 t c ? 4.0 25.2 ? ns 136 previous cas deassertion to ras deassertion t rhcp 6 t c ? 4.0 46.0 ? ns 137 cas assertion pulse width t cas 2.5 t c ? 4.0 16.8 ? ns 138 last cas deassertion to ras assertion 5 ? brw[1:0] = 00 t crp 2.75 t c ? 6.0 ? ? ns ? brw[1:0] = 01 4.25 t c ? 6.0 ? ? ? brw[1:0] = 10 5.25 t c ? 6.0 37.7 ? ? brw[1:0] = 11 7.25 t c ? 6.0 54.4 ? 139 cas deassertion pulse width t cp 2 t c ? 4.0 12.7 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 4.3 ? ns 141 cas assertion to column address not valid t cah 3.5 t c ? 4.0 25.2 ? ns 142 last column address valid to ras deassertion t ral 5 t c ? 4.0 37.7 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 4.0 6.4 ? ns 144 cas deassertion to wr assertion t rch 1.25 t c ? 4.0 6.4 ? ns 145 cas assertion to wr deassertion t wch 3.25 t c ? 4.2 22.9 ? ns 146 wr assertion pulse width t wp 4.5 t c ? 4.5 33.0 ? ns 147 last wr assertion to ras deassertion t rwl 4.75 t c ? 4.3 35.3 ? ns 148 wr assertion to cas deassertion t cwl 3.75 t c ? 4.3 26.9 ? ns 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.0 0.2 ? ns 150 cas assertion to data not valid (write) t dh 3.5 t c ? 4.0 25.2 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 6.1 ? ns 152 last rd assertion to ras deassertion t roh 4.5 t c ? 4.0 33.5 ? ns 153 rd assertion to data valid t ga 3.25 t c ? 7.0 ? 20.1 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 5.9 ? ns 156 wr deassertion to data high impedance 0.25 t c ?2.1ns
2-26 DSP56366 advance information motorola specifications external memory expansion port (port a) figure 2-12 dram page mode write accesses notes: 1. the number of wait states for pa ge mode access is specified in the dcr. 2. the refresh period is specified in the dcr. 3. the asynchronous delays specifie d in the expressions are valid for DSP56366 . 4. all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 3 t c for read-after-read or wr ite-after-write sequences). 5. brw[1:0] (dram control register bits) defines the number of wait states that should be inserted in each dram out-of-page access. 6. rd deassertion will al ways occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 2-12 dram page mode timings, four wait states 1, 2, 3 (continued) no. characteristics symbol expression min max ras cas a0?a17 wr rd d0?d23 column row data out data out data out last column column add address address address 136 135 131 139 141 137 140 142 147 144 151 148 146 155 156 150 138 145 143 149 aa0473
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-27 figure 2-13 dram page mode read accesses ras cas a0?a17 wr rd d0?d23 column last column column row data in data in data in add address address address 136 135 131 137 140 141 142 143 152 133 153 132 138 139 134 154 aa0474
2-28 DSP56366 advance information motorola specifications external memory expansion port (port a) figure 2-14 dram out-of-page wait states selection guide table 2-13 dram out-of-page and re fresh timings, four wait states 1, 2 no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max 157 random read or write cycle time t rc 5 t c 250.0 ? 166.7 ? ns 158 ras assertion to da ta valid (read) t rac 2.75 t c ? 7.5 ? 130.0 ? 84.2 ns 159 cas assertion to da ta valid (read) t cac 1.25 t c ? 7.5 ? 55.0 ? 34.2 ns 160 column address vali d to data valid (read) t aa 1.5 t c ? 7.5 ? 67.5 ? 42.5 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 162 ras deassertion to ras assertion t rp 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 163 ras assertion pulse width t ras 3.25 t c ? 4.0 158.5 ? 104.3 ? ns chip frequency (mhz) dram type (t rac ns) 100 80 70 50 66 80 100 4 wait states 8 wait states 11 wait states 15 wait states note:this figure should be use for primary selection. for exact and detailed timings see the following tables. 60 40 120 aa0475
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-29 164 cas assertion to ras deassertion t rsh 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 165 ras assertion to cas deassertion t csh 2.75 t c ? 4.0 133.5 ? 87.7 ? ns 166 cas assertion pulse width t cas 1.25 t c ? 4.0 58.5 ? 37.7 ? ns 167 ras assertion to cas assertion t rcd 1.5 t c 2 73.0 77.0 48.0 52.0 ns 168 ras assertion to column address valid t rad 1.25 t c 2 60.5 64.5 39.7 43.7 ns 169 cas deassertion to ras assertion t crp 2.25 t c ? 4.0 108.5 ? 71.0 ? ns 170 cas deassertion pulse width t cp 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 171 row address valid to ras assertion t asr 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 172 ras assertion to row address not valid t rah 1.25 t c ? 4.0 58.5 ? 37.7 ? ns 173 column address valid to cas assertion t asc 0.25 t c ? 4.0 8.5 ? 4.3 ? ns 174 cas assertion to column address not valid t cah 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 175 ras assertion to column address not valid t ar 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 176 column address valid to ras deassertion t ral 2 t c ? 4.0 96.0 ? 62.7 ? ns 177 wr deassertion to cas assertion t rcs 1.5 t c ? 3.8 71.2 ? 46.2 ? ns 178 cas deassertion to wr assertion t rch 0.75 t c ? 3.7 33.8 ? 21.3 ? ns 179 ras deassertion to wr assertion t rrh 0.25 t c ? 3.7 8.8 ? 4.6 ? ns 180 cas assertion to wr deassertion t wch 1.5 t c ? 4.2 70.8 ? 45.8 ? ns 181 ras assertion to wr deassertion t wcr 3 t c ? 4.2 145.8 ? 95.8 ? ns 182 wr assertion pulse width t wp 4.5 t c ? 4.5 220.5 ? 145.5 ? ns 183 wr assertion to ras deassertion t rwl 4.75 t c ? 4.3 233.2 ? 154.0 ? ns 184 wr assertion to cas deassertion t cwl 4.25 t c ? 4.3 208.2 ? 137.4 ? ns 185 data valid to cas assertion (write) t ds 2.25 t c ? 4.0 108.5 ? 71.0 ? ns 186 cas assertion to data not valid (write) t dh 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 187 ras assertion to data not valid (write) t dhr 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 188 wr assertion to cas assertion t wcs 3 t c ? 4.3 145.7 ? 95.7 ? ns table 2-13 dram out-of-page and re fresh timings, four wait states 1, 2 (continued) no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max
2-30 DSP56366 advance information motorola specifications external memory expansion port (port a) 189 cas assertion to ras assertion (refresh) t csr 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 1.25 t c ? 4.0 58.5 ? 37.7 ? ns 191 rd assertion to ras deassertion t roh 4.5 t c ? 4.0 221.0 ? 146.0 ? ns 192 rd assertion to data valid t ga 4 t c ? 7.5 ? 192.5 ? 125.8 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 37.2 ? 24.7 ? ns 195 wr deassertion to data high impedance 0.25 t c ? 12.5 ? 8.3 ns notes: 1. the number of wait states for out of page access is specified in the dcr. 2. the refresh period is specified in the dcr. 3. rd deassertion will al ways occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4. reduced dsp clock speed allows use of dram out-of-page access with four wait states (see figure 2-17 .). table 2-14 dram out-of-page and refresh timings, eight wait states 1, 2 no. characteristics 4 symbol expression 3 66 mhz 80 mhz unit min max min max 157 random read or write cycle time t rc 9 t c 136.4 ? 112.5 ? ns 158 ras assertion to da ta valid (read) t rac 4.75 t c ? 7.5 ? 64.5 ? ? ns 4.75 t c ? 6.5 ? ? ? 52.9 ns 159 cas assertion to da ta valid (read) t cac 2.25 t c ? 7.5 ? 26.6 ? ? ns 2.25 t c ? 6.5 ? ? ? 21.6 ns 160 column address vali d to data valid (read) t aa 3 t c ? 7.5 ? 40.0 ? ? ns 3 t c ? 6.5 ? ? ? 31.0 ns 161 cas deassertion to data not valid (read hold time) t off 0.0?0.0?ns 162 ras deassertion to ras assertion t rp 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 163 ras assertion pulse width t ras 5.75 t c ? 4.0 83.1 ? 67.9 ? ns 164 cas assertion to ras deassertion t rsh 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 165 ras assertion to cas deassertion t csh 4.75 t c ? 4.0 68.0 ? 55.5 ? ns 166 cas assertion pulse width t cas 2.25 t c ? 4.0 30.1 ? 24.1 ? ns 167 ras assertion to cas assertion t rcd 2.5 t c 2 35.9 39.9 29.3 33.3 ns 168 ras assertion to column address valid t rad 1.75 t c 2 24.5 28.5 19.9 23.9 ns table 2-13 dram out-of-page and re fresh timings, four wait states 1, 2 (continued) no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-31 169 cas deassertion to ras assertion t crp 4.25 t c ? 4.0 59.8 ? 49.1 ? ns 170 cas deassertion pulse width t cp 2.75 t c ? 4.0 37.7 ? 30.4 ? ns 171 row address valid to ras assertion t asr 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 172 ras assertion to row address not valid t rah 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.07.4?5.4?ns 174 cas assertion to column address not valid t cah 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 175 ras assertion to column address not valid t ar 5.75 t c ? 4.0 83.1 ? 67.9 ? ns 176 column address valid to ras deassertion t ral 4 t c ? 4.0 56.6 ? 46.0 ? ns 177 wr deassertion to cas assertion t rcs 2 t c ? 3.8 26.5 ? 21.2 ? ns 178 cas deassertion to wr 5 assertion t rch 1.25 t c ? 3.7 15.2 ? 11.9 ? ns 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 3.7 0.1 ? ? ? ns 0.25 t c ? 3.0 ? ? 0.1 ? ns 180 cas assertion to wr deassertion t wch 3 t c ? 4.2 41.3 ? 33.3 ? ns 181 ras assertion to wr deassertion t wcr 5.5 t c ? 4.2 79.1 ? 64.6 ? ns 182 wr assertion pulse width t wp 8.5 t c ? 4.5 124.3 ? 101.8 ? ns 183 wr assertion to ras deassertion t rwl 8.75 t c ? 4.3 128.3 ? 105.1 ? ns 184 wr assertion to cas deassertion t cwl 7.75 t c ? 4.3 113.1 ? 92.6 ? ns 185 data valid to cas assertion (write) t ds 4.75 t c ? 4.0 68.0 ? 55.4 ? ns 186 cas assertion to data not valid (write) t dh 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 187 ras assertion to data not valid (write) t dhr 5.75 t c ? 4.0 83.1 ? 67.9 ? ns 188 wr assertion to cas assertion t wcs 5.5 t c ? 4.3 79.0 ? 64.5 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 18.7 ? 14.8 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 191 rd assertion to ras deassertion t roh 8.5 t c ? 4.0 124.8 ? 102.3 ? ns 192 rd assertion to data valid t ga 7.5 t c ? 7.5 ? 106.1 ? ? ns 7.5 t c ? 6.5 ? ? ? 87.3 ns 193 rd deassertion to data not valid 4 t gz 0.0 0.0?0.0?ns 194 wr assertion to data active 0.75 t c ? 0.3 11.1 ? 9.1 ? ns 195 wr deassertion to data high impedance 0.25 t c ?3.8?3.1ns table 2-14 dram out-of-page and refresh timings, eight wait states 1, 2 (continued) no. characteristics 4 symbol expression 3 66 mhz 80 mhz unit min max min max
2-32 DSP56366 advance information motorola specifications external memory expansion port (port a) notes: 1. the number of wait states for out-of-page access is specified in the dcr. 2. the refresh period is specified in the dcr. 3. the asynchronous delays specified in the expressions are valid for DSP56366. 4. rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 5. either t rch or t rrh must be satisfied for read cycles. table 2-14 dram out-of-page and refresh timings, eight wait states 1, 2 (continued) no. characteristics 4 symbol expression 3 66 mhz 80 mhz unit min max min max
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-33 table 2-15 dram out-of-page and re fresh timings, eleven wait states 1, 2 no. characteristics 4 symbol expression 3 min max unit 157 random read or write cycle time t rc 12 t c 120.0 ? ns 158 ras assertion to data valid (read) t rac 6.25 t c ? 7.0 ? 55.5 ns 159 cas assertion to data valid (read) t cac 3.75 t c ? 7.0 ? 30.5 ns 160 column address valid to data valid (read) t aa 4.5 t c ? 7.0 ? 38.0 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 162 ras deassertion to ras assertion t rp 4.25 t c ? 4.0 38.5 ? ns 163 ras assertion pulse width t ras 7.75 t c ? 4.0 73.5 ? ns 164 cas assertion to ras deassertion t rsh 5.25 t c ? 4.0 48.5 ? ns 165 ras assertion to cas deassertion t csh 6.25 t c ? 4.0 58.5 ? ns 166 cas assertion pulse width t cas 3.75 t c ? 4.0 33.5 ? ns 167 ras assertion to cas assertion t rcd 2.5 t c 4.0 21.0 29.0 ns 168 ras assertion to column address valid t rad 1.75 t c 4.0 13.5 21.5 ns 169 cas deassertion to ras assertion t crp 5.75 t c ? 4.0 53.5 ? ns 170 cas deassertion pulse width t cp 4.25 t c ? 4.0 38.5 ? ns 171 row address valid to ras assertion t asr 4.25 t c ? 4.0 38.5 ? ns 172 ras assertion to row address not valid t rah 1.75 t c ? 4.0 13.5 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 3.5 ? ns 174 cas assertion to column address not valid t cah 5.25 t c ? 4.0 48.5 ? ns 175 ras assertion to column address not valid t ar 7.75 t c ? 4.0 73.5 ? ns 176 column address valid to ras deassertion t ral 6 t c ? 4.0 56.0 ? ns 177 wr deassertion to cas assertion t rcs 3.0 t c ? 4.0 26.0 ? ns 178 cas deassertion to wr 5 assertion t rch 1.75 t c ? 4.0 13.5 ? ns 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 2.0 0.5 ? ns 180 cas assertion to wr deassertion t wch 5 t c ? 4.2 45.8 ? ns 181 ras assertion to wr deassertion t wcr 7.5 t c ? 4.2 70.8 ? ns 182 wr assertion pulse width t wp 11.5 t c ? 4.5 110.5 ? ns 183 wr assertion to ras deassertion t rwl 11.75 t c ? 4.3 113.2 ? ns 184 wr assertion to cas deassertion t cwl 10.25 t c ? 4.3 103.2 ? ns 185 data valid to cas assertion (write) t ds 5.75 t c ? 4.0 53.5 ? ns 186 cas assertion to data not valid (write) t dh 5.25 t c ? 4.0 48.5 ? ns 187 ras assertion to data not valid (write) t dhr 7.75 t c ? 4.0 73.5 ? ns 188 wr assertion to cas assertion t wcs 6.5 t c ? 4.3 60.7 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 11.0 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 2.75 t c ? 4.0 23.5 ? ns 191 rd assertion to ras deassertion t roh 11.5 t c ? 4.0 111.0 ? ns
2-34 DSP56366 advance information motorola specifications external memory expansion port (port a) 192 rd assertion to data valid t ga 10 t c ? 7.0 ? 93.0 ns 193 rd deassertion to data not valid 4 t gz 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 7.2 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.5ns notes: 1. the number of wait states for out -of-page access is specified in the dcr. 2. the refresh period is specified in the dcr. 3. the asynchronous delays specified in the expressions are valid for DSP56366. 4. rd deassertion will al ways occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 5. either t rch or t rrh must be satisfied for read cycles. table 2-16 dram out-of-page and refresh timings, fifteen wait states 1, 2 no. characteristics 3 symbol expression min max unit 157 random read or write cycle time t rc 16 t c 133.3 ? ns 158 ras assertion to da ta valid (read) t rac 8.25 t c ? 5.7 ? 63.0 ns 159 cas assertion to da ta valid (read) t cac 4.75 t c ? 5.7 ? 33.9 ns 160 column address valid to data valid (read) t aa 5.5 t c ? 5.7 ? 40.1 ns 161 cas deassertion to data no t valid (read hold time) t off 0.0 0.0 ? ns 162 ras deassertion to ras assertion t rp 6.25 t c ? 4.0 48.1 ? ns 163 ras assertion pulse width t ras 9.75 t c ? 4.0 77.2 ? ns 164 cas assertion to ras deassertion t rsh 6.25 t c ? 4.0 48.1 ? ns 165 ras assertion to cas deassertion t csh 8.25 t c ? 4.0 64.7 ? ns 166 cas assertion pulse width t cas 4.75 t c ? 4.0 35.6 ? ns 167 ras assertion to cas assertion t rcd 3.5 t c 2 27.2 31.2 ns 168 ras assertion to column address valid t rad 2.75 t c 2 20.9 24.9 ns 169 cas deassertion to ras assertion t crp 7.75 t c ? 4.0 60.6 ? ns 170 cas deassertion pulse width t cp 6.25 t c ? 4.0 48.1 ? ns 171 row address valid to ras assertion t asr 6.25 t c ? 4.0 48.1 ? ns 172 ras assertion to row address not valid t rah 2.75 t c ? 4.0 18.9 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 2.2 ? ns 174 cas assertion to column address not valid t cah 6.25 t c ? 4.0 48.1 ? ns 175 ras assertion to column address not valid t ar 9.75 t c ? 4.0 77.2 ? ns 176 column address valid to ras deassertion t ral 7 t c ? 4.0 54.3 ? ns 177 wr deassertion to cas assertion t rcs 5 t c ? 3.8 37.9 ? ns 178 cas deassertion to wr 5 assertion t rch 1.75 t c ? 3.7 10.9 ? ns table 2-15 dram out-of-page and re fresh timings, eleven wait states 1, 2 (continued) no. characteristics 4 symbol expression 3 min max unit
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-35 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 2.0 0.1 ? ns 180 cas assertion to wr deassertion t wch 6 t c ? 4.2 45.8 ? ns 181 ras assertion to wr deassertion t wcr 9.5 t c ? 4.2 75.0 ? ns 182 wr assertion pulse width t wp 15.5 t c ? 4.5 124.7 ? ns 183 wr assertion to ras deassertion t rwl 15.75 t c ? 4.3 126.9 ? ns 184 wr assertion to cas deassertion t cwl 14.25 t c ? 4.3 114.4 ? ns 185 data valid to cas assertion (write) t ds 8.75 t c ? 4.0 68.9 ? ns 186 cas assertion to data not valid (write) t dh 6.25 t c ? 4.0 48.1 ? ns 187 ras assertion to data not valid (write) t dhr 9.75 t c ? 4.0 77.2 ? ns 188 wr assertion to cas assertion t wcs 9.5 t c ? 4.3 74.9 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 8.5 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 4.75 t c ? 4.0 35.6 ? ns 191 rd assertion to ras deassertion t roh 15.5 t c ? 4.0 125.2 ? ns 192 rd assertion to data valid t ga 14 t c ? 5.7 ? 111.0 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 5.9 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.1ns notes: 1. the number of wait states for out-of-page access is specified in the dcr. 2. the refresh period is specified in the dcr. 3. rd deassertion will alwa ys occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4. either t rch or t rrh must be satisfied for read cycles. table 2-16 dram out-of-page and re fresh timings, fifteen wait states 1, 2 (continued) no. characteristics 3 symbol expression min max unit
2-36 DSP56366 advance information motorola specifications external memory expansion port (port a) figure 2-15 dram out-of-page read access ras cas a0?a17 wr rd d0?d23 data row address column address in 157 163 165 162 162 169 170 171 168 167 164 166 173 174 175 172 177 176 191 160 168 159 193 161 192 158 179 aa0476
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-37 figure 2-16 dram out-of-page write access ras cas a0?a17 wr rd d0?d23 data out column address row address 162 163 165 162 157 169 170 167 168 164 166 171 173 174 176 172 181 175 180 188 182 184 183 187 185 194 186 195 aa0477
2-38 DSP56366 advance information motorola specifications external memory expansion port (port a) figure 2-17 dram refresh access ras cas wr 157 163 162 162 190 170 165 189 177 aa0478
specifications external memory expansion port (port a) motorola DSP56366 advance information 2-39 arbitration timings figure 2-18 asynchronous bus arbitration timing figure 2-19 asynchronous bus arbitration timing table 2-17 asynchronous bus arbitration timing no. characteristics expression 120 mhz unit min max 250 bb assertion window from bg input negation. 2 .5* tc + 5 ? 25.8 ns 251 delay from bb assertion to bg assertion 2 * tc + 5 21.7 ? ns comments: 1. bit 13 in the omr register must be set to enter asynchronous ar- bitration mode 2. if asynchronous arbitration mode is active, none of the timings in table 2-17 is required. 3. in order to guarantee timings 250, and 251, it is recommended to assert bg inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in figure 2-18 . bg1 bb 250 251 bg2 bg1 bg2 250+251
2-40 DSP56366 advance information motorola specifications external memory expansion port (port a) background explanation for asynchronous bus arbitration: the asynchronous bus arbitration is enabled by internal synchronization circuits on bg and bb inputs. these synchronization circuits add delay from the external signal until it is exposed to internal logic. as a result of this delay, a 56300 part may assume mastership and assert bb for some time after bg is negated. this is the reason for timing 250. once bb is asserted, there is a synchronization delay from bb assertion to the time this assertion is exposed to other 56300 components which ar e potential masters on the same bus. if bg input is asserted before that time, a situation of bg asserted, and bb negated, may cause another 56300 component to assume mastership at the same time. theref ore some non-overlap period between one bg input active to another bg input active is required. timing 251 en sures that such a situation is avoided.
specifications parallel host int erface (hdi08) timing motorola DSP56366 advance information 2-41 parallel host interface (hdi08) timing table 2-18 host interface (hdi08) timing 1, 2 no. characteristics 3 expression 120 mhz unit min max 317 read data strobe assertion width 4 hack read assertion width t c + 9.9 18.3 ? ns 318 read data strobe deassertion width 4 hack read deassertion width ?9.9?ns 319 read data strobe deassertion width 4 after ?last data register? reads 5,6 , or between two cons ecutive cvr, icr, or isr reads 7 hack deassertion width afte r ?last data register? reads 5,6 2.5 t c + 6.6 27.4 ? ns 320 write data strobe assertion width 8 hack write assertion width ? 13.2 ? ns 321 write data strobe deassertion width 8 hack write deassertion width ? after icr, cvr and ?last data register? writes 5 2.5 t c + 6.6 27.4 ? ns ? after ivr writes, or ? after txh:txm writes (with hbe=0), or ? after txl:txm writes (with hbe=1) 16.5 ? 322 has assertion width ? 9.9 ? ns 323 has deassertion to data strobe assertion 9 ?0.0?ns 324 host data input setup time before write data strobe deassertion 8 host data input se tup time before hack write deassertion ?9.9?ns 325 host data input hold time after write data strobe deassertion 8 host data input hol d time after hack write deassertion ?3.3?ns 326 read data strobe as sertion to output da ta active from high impedance 4 hack read assertion to output data active from high impedance ?3.3?ns 327 read data strobe assert ion to output data valid 4 hack read assertion to output data valid ??24.2ns 328 read data strobe deasse rtion to output data high impedance 4 hack read deassertion to output data high impedance ? ? 9.9 ns 329 output data hold time after read data strobe deassertion 4 output data hold time after hack read deassertion ?3.3?ns 330 hcs assertion to read da ta strobe deassertion 4 t c +9.9 18.2 ? ns 331 hcs assertion to write da ta strobe deassertion 8 ?9.9?ns 332 hcs assertion to output data valid ? ? 19.1 ns
2-42 DSP56366 advance information motorola specifications parallel host int erface (hdi08) timing 333 hcs hold time after data strobe deassertion 9 ?0.0?ns 334 address (ad7?ad0) setup time before has deassertion (hmux=1) ?4.7?ns 335 address (ad7?ad0) hold time after has deassertion (hmux=1) ?3.3?ns 336 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w setup time before data strobe assertion 9 ?read ?0? ns ? write 4.7 ? 337 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w hold time after data strobe deassertion 9 ?3.3?ns 338 delay from read data strobe deassertion to host request assertion for ?last data register? read 4, 5, 10 t c 8.3 ? ns 339 delay from write data strobe deassertion to host request assertion for ?last data register? write 5, 8, 10 2 t c 16.7 ? ns 340 delay from data strobe a ssertion to host request deassertion for ?last data register? read or write (hrod = 0) 5, 9, 10 ??19.1ns 341 delay from data strobe a ssertion to host request deassertion for ?last data register? read or write (hrod = 1, open drain host request) 5, 9, 10, 11 ? ? 300.0 ns 342 delay from dma hack deassertion to horeq assertion ns ? for ?last data register? read 5 2 t c + 19.1 35.8 ? ? for ?last data register? write 5 1.5 t c + 19.1 31.6 ? ? for other cases 0.0 ? 343 delay from dma hack assertion to ho req deassertion ? hrod = 0 5 ??20.2ns 344 delay from dma hack assertion to horeq deassertion for ?last data register? read or write ? hrod = 1, open drain host request 5, 11 ? ? 300.0 ns table 2-18 host interface (hdi08) timing 1, 2 (continued) no. characteristics 3 expression 120 mhz unit min max
specifications parallel host int erface (hdi08) timing motorola DSP56366 advance information 2-43 figure 2-20 host interrupt vector register (ivr) read timing diagram notes: 1. see host port usage considerations in the DSP56366 user?s manual. 2. in the timing diagrams below, the controls pins are drawn as active lo w. the pin polarity is programmable. 3. v cc = 3.3 v 0.16 v; t j = ?40c to +105c, c l = 50 pf 4. the read data strobe is hrd in the dual data strobe mode and hds in the single data strobe mode. 5. the ?last data register? is the register at addr ess $7, which is the last location to be read or written in data transfers. 6. this timing is applicable only if a read from the ?last data register? is followed by a read from the rxl, rxm, or rxh registers without first polling rxdf or hreq bits, or waiting for the assertion of the horeq signal. 7. this timing is applicable only if two cons ecutive reads from one of these registers are executed. 8. the write data strobe is hwr in the dual data strobe mode and hds in the single data strobe mode. 9. the data strobe is host read (hrd) or host write (hwr) in th e dual data strobe mode and host data strobe (hds) in the single data strobe mode. 10. the host request is horeq in the single ho st request mode and h rrq and htrq in the double host request mode. 11. in this calculation, the host re quest signal is pulled up by a 4.7 k ? resistor in the open-drain mode. table 2-18 host interface (hdi08) timing 1, 2 (continued) no. characteristics 3 expression 120 mhz unit min max hack hd7?hd0 horeq 329 317 318 328 326 327 aa1105
2-44 DSP56366 advance information motorola specifications parallel host int erface (hdi08) timing figure 2-21 read timing diagram, non-multiplexed bus hrd , hds ha0?ha2 hcs hd0?hd7 horeq , 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 aa0484 hrrq , htrq
specifications parallel host int erface (hdi08) timing motorola DSP56366 advance information 2-45 figure 2-22 write timing di agram, non-multiplexed bus hwr , hds ha0?ha2 hcs hd0?hd7 horeq , hrrq , htrq 336 331 337 321 320 324 325 339 340 341 333 aa0485
2-46 DSP56366 advance information motorola specifications parallel host int erface (hdi08) timing figure 2-23 read timing diagram, multiplexed bus hrd , hds ha8?ha10 has had0?had7 horeq , hrrq , htrq address data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 aa0486 322
specifications parallel host int erface (hdi08) timing motorola DSP56366 advance information 2-47 figure 2-24 write timing diagram, multiplexed bus figure 2-25 host dma write timing diagram hwr , hds ha8?ha10 horeq , hrrq , htrq has had0?had7 address data 320 321 325 324 335 341 339 336 334 340 322 323 aa0487 horeq (output) hack (input) h0?h7 (input) data valid txh/m/l write 320 321 343 342 324 344 325
2-48 DSP56366 advance information motorola specifications parallel host int erface (hdi08) timing figure 2-26 host dma read timing diagram 326 317 318 327 328 329 data valid horeq (output) hack (input) h0-h7 (output) rxh read 343 342 342
specifications serial host interfa ce spi protocol timing motorola DSP56366 advance information 2-49 serial host interface spi protocol timing table 2-19 serial host interface spi protocol timing no. characteristics 1 mode filter mode expression min max unit 140 tolerable spike width on clock or data in ? bypassed ? ? 0 ns narrow ? ? 50 ns wide ? ? 100 ns 141 minimum serial clock cycle = t spicc (min) master bypassed 6 t c +46 96 ? ns narrow 6 t c +152 202 ? ns wide 6 t c +223 273 ? ns 142 serial clock high period master bypassed 0.5 t spicc ?10 38 ? ns narrow 0.5 t spicc ?10 91 ? ns wide 0.5 t spicc ?10 126.5 ? ns slave bypassed 2.5 t c +12 32.8 ? ns narrow 2.5 t c +102 122.8 ? ns wide 2.5 t c +189 209.8 ? ns 143 serial clock low period master bypassed 0.5 t spicc ?10 38 ? ns narrow 0.5 t spicc ?10 91 ? ns wide 0.5 t spicc ?10 126.5 ? ns slave bypassed 2.5 t c +12 32.8 ? ns narrow 2.5 t c +102 122.8 ? ns wide 2.5 t c +189 209.8 ? ns 144 serial clock rise/fall time master ? ? ? 10 ns slave ? ? ? 2000 ns 146 ss assertion to first sck edge cpha = 0 slave bypassed 3.5 t c +15 44.2 ? ns narrow 0 0 ? ns wide 0 0 ? ns cpha = 1 slave bypassed 10 10 ? ns narrow 0 0 ? ns wide 0 0 ? ns 147 last sck edge to ss not asserted slave bypassed 12 12 ? ns narrow 102 102 ? ns wide 189 189 ? ns 148 data input valid to sc k edge (data input set- up time) master/ slave bypassed 0 0 ? ns narrow max{(20-t c ), 0} 11.7 ? ns wide max{(40-t c ), 0} 31.7 ? ns
2-50 DSP56366 advance information motorola specifications serial host interfa ce spi protocol timing 149 sck last sampling edge to data input not valid master/ slave bypassed 2.5 t c +10 30.8 ? ns narrow 2.5 t c +30 50.8 ? ns wide 2.5 t c +50 70.8 ? ns 150 ss assertion to data out active slave ? 2 2 ? ns 151 ss deassertion to da ta high impedance 2 slave ? 9 ? 9 ns 152 sck edge to data out valid (data out delay time) master/ slave bypassed 2 t c +33 ? 49.7 ns narrow 2 t c +123 ? 139.7 ns wide 2 t c +210 ? 226.7 ns 153 sck edge to data out not valid (data out hold time) master/ slave bypassed t c +5 13.3 ? ns narrow t c +55 63.3 ? ns wide t c +106 114.3 ? ns 154 ss assertion to data out valid (cpha = 0) slave ? t c +33 ? 41.3 ns 157 first sck sampling edge to hreq output deassertion slave bypassed 2.5 t c +30 ? 50.8 ns narrow 2.5 t c +120 ? 140.8 ns wide 2.5 t c +217 ? 237.8 ns 158 last sck sampling edge to hreq output not deasserted (cpha = 1) slave bypassed 2.5 t c +30 50.8 ? ns narrow 2.5 t c +80 100.8 ? ns wide 2.5 t c +136 156.8 ? ns 159 ss deassertion to hreq output not deasserted (cpha = 0) slave ? 2.5 t c +30 50.8 ? ns 160 ss deassertion pulse width (cpha = 0) slave ? t c +6 14.3 ? ns 161 hreq in assertion to first sck edge master bypassed 0.5 t spicc + 2.5 t c +43 111.8 ? ns narrow 0.5 t spicc + 2.5 t c +43 164.8 ? ns wide 0.5 t spicc + 2.5 t c +43 200.3 ? ns 162 hreq in deassertion to last sck sampling edge (hreq in set-up time) (cpha = 1) master ? 0 0 ? ns 163 first sck edge to hreq in not asserted (hreq in hold time) master ? 0 0 ? ns notes: 1. v cc = 3.16 v 0.16 v; t j = ?40c to +105c, c l = 50 pf 2. periodically sampled, not 100% tested table 2-19 serial host interface spi protocol timing (continued) no. characteristics 1 mode filter mode expression min max unit
specifications serial host interfa ce spi protocol timing motorola DSP56366 advance information 2-51 figure 2-27 spi master timing (cpha = 0) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 149 149 148 152 153 163 161 aa0271
2-52 DSP56366 advance information motorola specifications serial host interfa ce spi protocol timing figure 2-28 spi master timing (cpha = 1) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 148 149 152 153 163 161 162 149 aa0272
specifications serial host interfa ce spi protocol timing motorola DSP56366 advance information 2-53 figure 2-29 spi slave timing (cpha = 0) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 141 144 144 143 142 154 150 152 153 148 149 159 157 153 151 valid valid 148 149 147 160 146 aa0273
2-54 DSP56366 advance information motorola specifications serial host interfa ce spi protocol timing figure 2-30 spi slave timing (cpha = 1) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 144 144 143 142 150 152 148 149 158 153 151 valid valid 148 147 146 152 149 157 aa0274
specifications serial host interface (shi) i 2 c protocol timing motorola DSP56366 advance information 2-55 serial host interface (shi) i 2 c protocol timing table 2-20 shi i 2 c protocol timing no. characteristics 1,2,3 symbol/ expression standard mode 4 fast mode 5 unit min max min max tolerable spike width on scl or sda ? filters bypassed ?0 ? 0ns narrow filters enabled ? 50 ? 50 ns wide filters enabled ? 100 ? 100 ns 171 scl clock frequency f scl ? 100 ? 400 khz 171 scl clock cycle t scl 10 ? 2.5 ? s 172 bus free time t buf 4.7 ? 1.3 ? s 173 start condition set-up time t su;sta 4.7 ? 0.6 ? s 174 start condition hold time t hd;sta 4.0 ? 0.6 ? s 175 scl low period t low 4.7 ? 1.3 ? s 176 scl high period t high 4.0 ? 1.3 ? s 177 scl and sda rise time t r ? 1000 20 + 0.1 c b 300 ns 178 scl and sda fall time t f ? 300 20 + 0.1 c b 300 ns 179 data set-up time t su;dat 250 ? 100 ? ns 180 data hold time t hd;dat 0.0 ? 0.0 0.9 s 181 dsp clock frequency f dsp filters bypassed 10.6 ? 28.5 ? mhz narrow filters enabled 11.8 ? 39.7 ? mhz wide filters enabled 13.1 ? 61.0 ? mhz 182 scl low to data out valid t vd;dat ? 3.4 ? 0.9 s 183 stop condition set-up time t su;sto 4.0 ? 0.6 ? s 184 hreq in deassertion to last scl edge (hreq in set-up time) t su;rqi 0.0 ? 0.0 ? ns 186 first scl sampling edge to hreq output deassertion t ng;rqo ns filters bypassed 2 t c + 30 ? 46.7 ? 46.7 narrow filters enabled 2 t c + 120 ? 136.7 ? 136.7 wide filters enabled 2 t c + 208 ? 224.7 ? 224.7 187 last scl edge to hreq output not deasserted t as;rqo ns filters bypassed 2 t c + 30 46.7 ? 46.7 ? narrow filters enabled 2 t c + 80 96.7 ? 96.7 ? wide filters enabled 2 t c + 135 151.6 ? 151.6 ?
2-56 DSP56366 advance information motorola specifications serial host interface (shi) i 2 c protocol timing programming the serial clock the programmed serial clock cycle, t i 2 ccp , is specified by the value of the hdm[7:0] and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is t i 2 ccp = [t c 2 (hdm[7:0] + 1) (7 (1 ? hrs) + 1)] where ? hrs is the prescaler rate select bit. when hrs is cleared, the fixed divide-by-eight prescaler is operational. when hrs is set, the prescaler is bypassed. ? hdm[7:0] are the divider modulus select bits. a divide ratio from 1 to 256 (hdm[7:0] = $00 to $ff) may be selected. in i 2 c mode, the user may select a value fo r the programmed serial clock cycle from 6 t c (if hdm[7:0] = $02 and hrs = 1) to 4096 t c (if hdm[7:0] = $ff and hrs = 0) 188 hreq in assertion to first scl edge t as;rqi 0.5 t i 2 ccp - 0.5 t c - 21 ns filters bypassed 4440 ? 1041 ? narrow filters enabled 4373 ? 999 ? wide filters enabled 4373 ? 958 ? 189 first scl edge to hreq in not asserted (hreq in hold time) t ho;rqi 0.0 ? 0.0 ? ns notes: 1. v cc = 3.16 v 0.16 v; t j = ?40c to +105c 2. pull-up resistor: r p (min) = 1.5 kohm 3. capacitive load: c b (max) = 400 pf 4. it is recommended to enable the wide filters when operating in the i 2 c standard mode. 5. it is recommended to enable the narrow filters when operating in the i 2 c fast mode. table 2-20 shi i 2 c protocol timing (continued) no. characteristics 1,2,3 symbol/ expression standard mode 4 fast mode 5 unit min max min max
specifications serial host interface (shi) i 2 c protocol timing motorola DSP56366 advance information 2-57 the programmed serial clock cycle (t i 2 ccp ), scl rise time (t r ), and the filters selec ted should be chosen in order to achieve the desi red scl serial clock cycle (t scl ), as shown in table 2-21. example: for dsp clock frequency of 120 mhz (i.e. t c = 8.33ns), operating in a standard mode i 2 c environment (f scl = 100 khz (i.e. t scl = 10 s), t r = 1000ns), with wide filters enabled: t i 2 ccp = 10 s - 2.5 8.33ns - 223ns - 1000ns = 8756ns choosing hrs = 0 gives hdm[7:0] = 8756ns / (2 8.33ns 8) - 1 = 64.67 thus the hdm[7:0] value should be programmed to $41 (=65). the resulting t i 2 ccp will be: t i 2 ccp = [t c 2 (hdm[7:0] + 1) (7 (1 ? hrs) + 1)] t i 2 ccp = [8.33ns 2 (65 + 1) (7 (1 ? 0) + 1)] t i 2 ccp = [8.33ns 2 66 8] = 8796.48ns table 2-21 scl serial clock cycle (t scl ) generated as master filters bypassed t i 2 ccp + 2.5 t c + 45ns + t r narrow filters enabled t i 2 ccp + 2.5 t c + 135ns + t r wide filters enabled t i 2 ccp + 2.5 t c + 223ns + t r
2-58 DSP56366 advance information motorola specifications serial host interface (shi) i 2 c protocol timing figure 2-31 i 2 c timing start scl hreq sda ack msb lsb stop 171 stop 173 176 175 177 178 180 179 172 186 182 183 189 174 188 184 187 aa0275
specifications enhanced serial audio interface timing motorola DSP56366 advance information 2-59 enhanced serial audi o interface timing table 2-22 enhanced serial audio interface timing no. characteristics 1, 2, 3 symbol expression min max cond- ition 4 unit 430 clock cycle 5 t ssicc 4 t c 33.3 ? i ck ns 3 t c 25.0 ? x ck txc:max[3*tc; t454] 27.2 ? x ck 431 clock high period ? for internal clock ?2 t c ? 10.0 6.7 ? ns ? for external clock 1.5 t c 12.5 ? 432 clock low period ? for internal clock ?2 t c ? 10.0 6.7 ? ns ? for external clock 1.5 t c 12.5 ? 433 rxc rising edge to fsr out (bl) high ?? ? ? 37.0 22.0 x ck i ck a ns 434 rxc rising edge to fsr out (bl) low ?? ? ? 37.0 22.0 x ck i ck a ns 435 rxc rising edge to fsr out (wr) high 6 ?? ? ? 39.0 24.0 x ck i ck a ns 436 rxc rising edge to fsr out (wr) low 6 ?? ? ? 39.0 24.0 x ck i ck a ns 437 rxc rising edge to fsr out (wl) high ?? ? ? 36.0 21.0 x ck i ck a ns 438 rxc rising edge to fsr out (wl) low ?? ? ? 37.0 22.0 x ck i ck a ns 439 data in setup time before rxc (sck in synchronous mode) falling edge ?? 0.0 19.0 ? ? x ck i ck ns 440 data in hold time af ter rxc falling edge ?? 5.0 3.0 ? ? x ck i ck ns 441 fsr input (bl, wr) high be fore rxc falling edge 6 ?? 23.0 1.0 ? ? x ck i ck a ns 442 fsr input (wl) high be fore rxc falling edge ?? 1.0 23.0 ? ? x ck i ck a ns 443 fsr input hold time af ter rxc falling edge ?? 3.0 0.0 ? ? x ck i ck a ns 444 flags input setup befo re rxc falling edge ? ? 0.0 19.0 ? ? x ck i ck s ns 445 flags input hold time after rxc falling edge ?? 6.0 0.0 ? ? x ck i ck s ns 446 txc rising edge to fst out (bl) high ?? ? ? 29.0 15.0 x ck i ck ns 447 txc rising edge to fst out (bl) low ?? ? ? 31.0 17.0 x ck i ck ns 448 txc rising edge to fst out (wr) high 6 ?? ? ? 31.0 17.0 x ck i ck ns 449 txc rising edge to fst out (wr) low 6 ?? ? ? 33.0 19.0 x ck i ck ns
2-60 DSP56366 advance information motorola specifications enhanced serial au dio interface timing 450 txc rising edge to fst out (wl) high ?? ? ? 30.0 16.0 x ck i ck ns 451 txc rising edge to fst out (wl) low ?? ? ? 31.0 17.0 x ck i ck ns 452 txc rising edge to data out enable from high impedance ?? ? ? 31.0 17.0 x ck i ck ns 453 txc rising edge to transmitter #0 drive enable assertion ?? ? ? 34.0 20.0 x ck i ck ns 454 txc rising edge to data out valid ? 23 + 0.5 t c 21.0 ? ? 27.2 21.0 x ck i ck ns 455 txc rising edge to data out high impedance 7 ?? ? ? 31.0 16.0 x ck i ck ns 456 txc rising edge to transmitter #0 drive enable deassertion 7 ?? ? ? 34.0 20.0 x ck i ck ns 457 fst input (bl, wr) setup time before txc falling edge 6 ?? 2.0 21.0 ? ? x ck i ck ns 458 fst input (wl) to data out enable from high impedance ? ? ? 27.0 ? ns 459 fst input (wl) to transmitter #0 drive enable assertion ? ? ? 31.0 ? ns 460 fst input (wl) setup time before txc falling edge ?? 2.0 21.0 ? ? x ck i ck ns 461 fst input hold time after txc falling edge ?? 4.0 0.0 ? ? x ck i ck ns 462 flag output valid after txc rising edge ?? ? ? 32.0 18.0 x ck i ck ns 463 hckr/hckt clock cycle ? ? 40.0 ? ns 464 hckt input rising edge to txc output ? ? ? 27.5 ns 465 hckr input rising edge to rxc output ? ? ? 27.5 ns table 2-22 enhanced serial a udio interface timing (continued) no. characteristics 1, 2, 3 symbol expression min max cond- ition 4 unit
specifications enhanced serial audio interface timing motorola DSP56366 advance information 2-61 notes: 1. v cc = 3.16 v 0.16 v; t j = ?40c to +105c, c l = 50 pf 2. i ck = internal clock x ck = external clock i ck a = internal cl ock, asynchronous mode (asynchronous implies that txc an d rxc are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that txc and rxc are the same clock) 3. bl = bit length wl = word length wr = word length relative 4. txc(sckt pin) = transmit clock rxc(sckr pin) = receive clock fst(fst pin) = tr ansmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receive high frequency clock 5. for the internal clock, the external clock cycle is defined by icyc and th e esai control register. 6. the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, bu t spreads from one serial clock before firs t bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. periodically sampled and not 100% tested table 2-22 enhanced serial audio interface timing (continued) no. characteristics 1, 2, 3 symbol expression min max cond- ition 4 unit
2-62 DSP56366 advance information motorola specifications enhanced serial au dio interface timing figure 2-32 esai transmitter timing last bit see note txc (input/output) fst (bit) out fst (word) out data out transmitter #0 drive enable fst (bit) in fst (word) in flags out note: in network mode, output flag transitions can occur at the st art of each time slot within the frame. in normal mode, the output flag stat e is asserted for the entire frame period. first bit 430 432 446 447 450 451 455 454 454 452 459 456 453 461 457 458 460 461 462 431 aa0490
specifications enhanced serial audio interface timing motorola DSP56366 advance information 2-63 figure 2-33 esai receiver timing rxc (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in last bit first bit 430 432 433 437 438 440 439 443 441 442 443 445 444 431 434 aa0491
2-64 DSP56366 advance information motorola specifications enhanced serial au dio interface timing figure 2-34 esai hckt timing figure 2-35 esai hckr timing hckt sckt(output) 464 463 hckr sckr (output) 465 463
specifications digital audio transmitter timing motorola DSP56366 advance information 2-65 digital audio transmitter timing figure 2-36 digital audio transmitter timing table 2-23 digital audio transmitter timing no. characteristic expression 120 mhz unit min max aci frequency (see note) 1 / (2 x t c ) ? 60 mhz 220 aci period 2 t c 16.7 ? ns 221 aci high duration 0.5 t c 4.2 ? ns 222 aci low duration 0.5 t c 4.2 ? ns 223 aci rising edge to ado valid 1.5 t c ? 12.5 ns note: in order to assure proper operation of the dax, the aci frequency should be less than 1/2 of the DSP56366 internal clock frequ ency. for example, if the DSP56366 is running at 120 mhz internally, the aci frequency should be less than 60 mhz. aci ado 220 223 aa1280 221 222
2-66 DSP56366 advance information motorola specifications timer timing timer timing figure 2-37 tio timer event input restrictions table 2-24 timer timing no. characteristics expression 120 mhz unit min max 480 tio low 2 t c + 2.0 18.7 ? ns 481 tio high 2 t c + 2.0 18.7 ? ns note: v cc = 3.3 v 0.16 v; t j = ?40c to +105c, c l = 50 pf tio 481 480 aa0492
specifications gpio timing motorola DSP56366 advance information 2-67 gpio timing figure 2-38 gpio timing table 2-25 gpio timing no. characteristics 1 expression min max unit 490 2 extal edge to gpio out valid (gpio out delay time) ? 32.8 ns 491 extal edge to gpio out not valid (gpio out hold time) 4.8 ? ns 492 gpio in valid to extal edge (gpio in set-up time) 10.2 ? ns 493 extal edge to gpio in not valid (gpio in hold time) 1.8 ? ns 494 2 fetch to extal edge before gpio change 6.75 t c -1.8 54.5 ? ns 495 gpio out rise time ? ? 13 ns 496 gpio out fall time ? ? 13 ns notes: 1. v cc = 3.3 v 0.16 v; t j = ?40c to +105c, c l = 50 pf 2. valid only when pll enabled with multiplication factor equal to one. valid gpio (input) gpio (output) extal (input) fetch the instruction move x0,x:(r0); x0 contains the new value of gpio and r0 contains the address of gpio data register. a0?a17 490 491 492 494 493 gpio (output) 495 496
2-68 DSP56366 advance information motorola specifications jtag timing jtag timing figure 2-39 test clock input timing diagram table 2-26 jtag timing no. characteristics all frequencies unit min max 500 tck frequency of operation (1/(t c 3); maximum 22 mhz) 0.0 22.0 mhz 501 tck cycle time in crystal mode 45.0 ? ns 502 tck clock pulse width measured at 1.5 v 20.0 ? ns 503 tck rise and fall times 0.0 3.0 ns 504 boundary scan input data setup time 5.0 ? ns 505 boundary scan input data hold time 24.0 ? ns 506 tck low to output data valid 0.0 40.0 ns 507 tck low to output high impedance 0.0 40.0 ns 508 tms, tdi data setup time 5.0 ? ns 509 tms, tdi data hold time 25.0 ? ns 510 tck low to tdo data valid 0.0 44.0 ns 511 tck low to tdo high impedance 0.0 44.0 ns notes: 1. v cc = 3.3 v 0.16 v; t j = ?40c to +105c, c l = 50 pf 2. all timings apply to once module data transfers because it uses the jtag port as an interface. tck (input) v m v m v ih v il 501 502 502 503 503 aa0496
specifications jtag timing motorola DSP56366 advance information 2-69 figure 2-40 boundary scan (jtag) timing diagram figure 2-41 test access port timing diagram tck (input) data inputs data outputs data outputs data outputs v ih v il input data valid output data valid output data valid 505 504 506 507 506 aa0497 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) v ih v il input data valid output data valid output data valid tms 508 509 510 511 510 aa0498
2-70 DSP56366 advance information motorola specifications jtag timing
motorola DSP56366 advance information 3-1 section 3 packaging pin-out and pack age information this section provides information ab out the available package for this product, including diagrams of the package pinouts and tables describi ng how the signals described in section 1 are allocated for the package. the DSP56366 is available in a 144-pin lqfp package. table 3-1 and table 3-2 show the pin/name assignments for the packages. lqfp package description top view of the 144-pin lqfp package is shown in figure 3-1 with its pin-outs. the package drawing is shown in figure 3-2 .
3-2 DSP56366 advance information motorola packaging pin-out and package information figure 3-1 144-pin package 108 d6 107 d5 106 d4 105 d3 104 gndd 103 vccd 102 d2 101 d1 100 d0 99 a17 98 a16 97 a15 96 gnda 95 vccqh 94 a14 93 a13 92 a12 91 vccql 90 gndq 89 a11 88 a10 87 gnda 86 vcca 85 a9 84 a8 83 a7 82 a6 81 gnda 80 vcca 79 a5 78 a4 77 a3 76 a2 75 gnda 74 vcca 73 a1 had4 37 vcch 38 gndh 38 had3 40 had2 41 had1 42 had0 43 reset# 44 vccp 45 pcap 46 gndp 47 sdo5_1/sdi0_1 48 vccqh 49 fst_1 50 aa2 51 cas# 52 sckt_1 53 gndq 54 extal 55 vccql 56 vccc 57 gndc 58 fsr_1 59 sckr_1 60 pinit/nmi# 61 ta# 62 br# 63 bb# 64 vccc 65 gndc 66 wr# 67 rd# 68 aa1 69 aa0 70 bg# 71 a0 72 sck/scl 1 ss#/ha2 2 hreq# 3 sdo0/sdo0_1 4 sdo1/sdo1_1 5 sdo2/sdi3/sdo2_1/sdi3_1 6 sdo3/sdi2/sdo3_1/sdi2_1 7 vccs 8 gnds 9 sdo4/sdi1 10 sdo5/sdi0 11 fst 12 fsr 13 sckt 14 sckr 15 hckt 16 hckr 17 vccql 18 gndq 19 vccqh 20 hds/hwr 21 hrw/hrd 22 hack/hrrq 23 horeq/htrq 24 vccs 25 gnds 26 ado 27 aci 28 tio0 29 hcs/ha10 30 ha9/ha2 31 ha8/ha1 32 has/ha0 33 had7 34 had6 35 had5 36 144 miso/sda 143 mosi/ha0 142 tms 141 tck 140 tdi 139 tdo 138 sdo4_1/sdi1_1 137 moda/irqa# 136 modb/irqb# 135 modcirqc# 134 modd/irqd# 133 d23 132 d22 131 d21 130 gndd 129 vccd 128 d20 127 gndq 126 vccql 125 d19 124 d18 123 d17 122 d16 121 d15 120 gndd 119 vccd 118 d14 117 d13 116 d12 115 d11 114 d10 113 d9 112 gndd 111 vccd 110 d8 109 d7
packaging pin-out and package information motorola DSP56366 advance information 3-3 table 3-1 signal identification by name signal name pin no. signal name pin no. signal name pin no. signal name pin no. a0 72 d9 113 gnds 9 sdo0/sdo0_1 4 a1 73 d10 114 gnds 26 sdo1/sdo1_1 5 a2 76 d11 115 ha8/ha1 32 sdo2/sdi3/sdo2_1/sdi3_1 6 a3 77 d12 116 ha9/ha2 31 sdo3/sdi2/sdo3_1/sdi2_1 7 a4 78 d13 117 hack/hrrq 23 sdo4/sdi1 10 a5 79 d14 118 had0 43 sdo4_1/sdi1_1 138 a6 82 d15 121 had1 42 sdo5/sdi0 11 a7 83 d16 122 had2 41 sdo5_1/sdi0_1 48 a8 84 d17 123 had3 40 ss#/ha2 2 a9 85 d18 124 had4 37 ta# 62 a10 88 d19 125 had5 36 tck 141 a11 89 d20 128 had6 35 tdi 140 a12 92 d21 131 had7 34 tdo 139 a13 93 d22 132 has/ha0 33 tio0 29 a14 94 d23 133 hckr 17 tms 142 a15 97 extal 55 hckt 16 vcca 74 a16 98 fsr 13 hcs/ha10 30 vcca 80 a17 99 fsr_1 59 hds/hwr 21 vcca 86 aa0 70 fst 12 horeq/htrq 24 vccc 57 aa1 69 fst_1 50 hreq# 3 vccc 65 aa2 51 gnda 75 hrw/hrd 22 vccd 103 aci 28 gnda 81 moda/irqa# 137 vccd 111 ado 27 gnda 87 modb/irqb# 136 vccd 119 bb# 64 gnda 96 modc/irqc# 135 vccd 129 bg# 71 gndc 58 modd/irqd# 134 vcch 38 br# 63 gndc 66 miso/sda 144 vccqh 20 cas# 52 gndd 104 mosi/ha0 143 vccqh 95 d0 100 gndd 112 pcap 46 vccqh 49 d1 101 gndd 120 pinit/nmi# 61 vccql 18 d2 102 gndd 130 rd# 68 vccql 56 d3 105 gndh 39 reset# 44 vccql 91 d4 106 gndp 47 sck/scl 1 vccql 126 d5 107 gndq 19 sckr 15 vccp 45 d6 108 gndq 54 sckr_1 60 vccs 8 d7 109 gndq 90 sckt 14 vccs 25 d8 110 gndq 127 sckt_1 53 wr# 67 table 3-2 signal identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 sck/scl 37 had4 73 a1 109 d7 2 ss#/ha2 38 vcch 74 vcca 110 d8 3 hreq# 39 gndh 75 gnda 111 vccd 4 sdo0/sdo0_1 40 had3 76 a2 112 gndd
3-4 DSP56366 advance information motorola packaging pin-out and package information 5 sdo1/sdo1_1 41 had2 77 a3 113 d9 6 sdo2/sdi3/sdo2_1/ sdi3_1 42 had1 78 a4 114 d10 7 sdo3/sdi2/sdo3_1/ sdi2_1 43 had0 79 a5 115 d11 8 vccs 44 reset# 80 vcca 116 d12 9 gnds 45 vccp 81 gnda 117 d13 10 sdo4/sdi1 46 pcap 82 a6 118 d14 11 sdo5/sdi0 47 gndp 83 a7 119 vccd 12 fst 48 sdo5_1/sdi0_1 84 a8 120 gndd 13 fsr 49 vccqh 85 a9 121 d15 14 sckt 50 fst_1 86 vcca 122 d16 15 sckr 51 aa2 87 gnda 123 d17 16 hckt 52 cas# 88 a10 124 d18 17 hckr 53 sckt_1 89 a11 125 d19 18 vccql 54 gndq 90 gndq 126 vccql 19 gndq 55 extal 91 vccql 127 gndq 20 vccqh 56 vccql 92 a12 128 d20 21 hds/hwr 57 vccc 93 a13 129 vccd 22 hrw/hrd 58 gndc 94 a14 130 gndd 23 hack/hrrq 59 fsr_1 95 vccqh 131 d21 24 horeq/htrq 60 sckr_1 96 gnda 132 d22 25 vccs 61 pinit/nmi# 97 a15 133 d23 26 gnds 62 ta# 98 a16 134 modd/irqd# 27 ado 63 br# 99 a17 135 modc/irqc# 28 aci 64 bb# 100 d0 136 modb/irqb# 29 tio0 65 vccc 101 d1 137 moda/irqa# 30 hcs/ha10 66 gndc 102 d2 138 sdo4_1/sdi1_1 31 ha9/ha2 67 wr# 103 vccd 139 tdo 32 ha8/ha1 68 rd# 104 gndd 140 tdi 33 has/ha0 69 aa1 105 d3 141 tck 34 had7 70 aa0 106 d4 142 tms 35 had6 71 bg# 107 d5 143 mosi/ha0 36 had5 72 a0 108 d6 144 miso/sda table 3-2 signal identification by pin number (continued)
packaging pin-out and package information motorola DSP56366 advance information 3-5 lqfp package mech anical drawing figure 3-2 DSP56366 144-pin lqfp package
3-6 DSP56366 advance information motorola packaging ordering drawings ordering drawings the detailed package drawi ng is available on the motorola web page at: http://www.mot-sps.c om/cgi-bin/cases.pl use package 918-03 for the search.
motorola DSP56366 advance information 4-1 section 4 design considerations thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the following equation: where: t a = ambient temperature c r qja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package w historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance. where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and cannot be influenced by the user. the user controls th e thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb), or otherwise change the thermal dissip ation capability of the area surroun ding the device on a pcb. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambien t environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional mode ling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a sy stem level model may be appropriate. a complicating factor is the existence of three comm on ways for determining the junction-to-case thermal resistance in plastic packages. ? to minimize temperature variation across the surfa ce, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. t j t a p d r ja () + = r ja r jc r ca + =
4-2 DSP56366 advance information motorola design considerations electrical design considerations ? to define a value approximately equal to a ju nction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. ? if the temperature of the package case (t t ) is determined by a th ermocouple, the thermal resistance is computed using th e value obtained by the equation (t j ? t t )/p d . as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also su itable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estim ate junction temperature from a thermocouple reading on the case of the package will estimate a junction temp erature slightly hotter than actual temperature. hence, the new thermal metric, ther mal characterization parameter or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that su rface temperature readings of packages are subject to significant errors caused by inad equate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommend ed technique is to attach a 40-gau ge thermocouple wire and bead to the top center of the package w ith thermally conductive epoxy. electrical design considerations use the following list of recommendati ons to assure correct dsp operation: ? provide a low-impedance path from the board power supply to each v cc pin on the dsp and from the board ground to each gnd pin. ? use at least six 0.01?0.1 f bypass capacitors positioned as close as possible to the four sides of the package to connect the v cc power source to gnd. ? ensure that capacitor leads and associated printe d circuit traces that connect to the chip v cc and gnd pins are less than 1.2 cm (0.5 inch) per capacitor lead. ? use at least a four-layer pc b with two inner layers for v cc and gnd. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields. however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). the suggested value for a pullup or pulldown resistor is 10 kohm.
design considerations power consumption considerations motorola DSP56366 advance information 4-3 ? because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. this recommendation particular ly applies to the address an d data buses as well as the irqa , irqb , irqc , irqd , ta and bg pins. maximum pcb trace lengths on the order of 15 cm (6 inches) are recommended. ? consider all device loads as we ll as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v cc and gnd circuits. ? all inputs must be terminated (i .e., not allowed to float) using cmos levels, excep t for the three pins with internal pull-up resistors (tms, tdi, tck ). ? take special care to minimize noise levels on the v ccp and gnd p pins. ? if multiple DSP56366 devices are on the same boar d, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. ? reset must be asserted when the chip is powered up. a stable extal signal must be supplied while reset is being asserted. ? at power-up, ensure that the voltage difference between the 5 v tolerant pins and the chip v cc never exceeds 3.95 v. power consumption considerations power dissipation is a key issue in portable dsp app lications. some of the factors which affect current consumption are described in this se ction. most of the current consumed by cmos devices is alternating current (ac), which is charging and discharging th e capacitances of the pins and internal nodes. current consumption is describ ed by the following formula: where c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle example 1 current consumption for a port a address pin loaded with 50 pf capacitance, ope rating at 3.3 v, and with a 1 20 mhz clock, toggling at its maximum possible rate (60 mhz), the current consumption is icvf = i5010 12 ? 3.3 60 10 6 9.9ma ==
4-4 DSP56366 advance information motorola design considerations pll performance issues the maximum internal current (i cci max) value reflects the typical poss ible switching of the internal buses on best-case operatio n conditions, which is not nec essarily a real application case. the typical internal current (i ccityp ) value reflects the average switching of the in ternal buses on typica l operating conditions. for applications that require very low current consumption, do the following: ? set the ebd bit when not accessing external memory. ? minimize external memory accesses and use internal memory accesses. ? minimize the number of pins that are switching. ? minimize the capacitive load on the pins. ? connect the unused inputs to pull-up or pull-down resistors. ? disable unused peripherals. one way to evaluate power consum ption is to use a current per mi ps measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the dsp). a benchmark power consumption t est algorithm is listed in appendix a . use the test algorithm, specific test current measurements, and the following equation to derive the current per mips value. where : i typf2 = current at f2 i typf1 = current at f1 f2 = high frequency (any specified operating frequency) f1 = low frequency (any specified op erating frequency lower than f2) note: f1 should be significantly less than f2. for example, f2 could be 66 mhz and f1 could be 33 mhz. the degree of difference between f1 and f2 determines the amount of precision with which the current ratin g can be determined for an application. pll performance issues the following explan ations should be considered as genera l observations on expected pll behavior. there is no testing that verifies these exact number s. these observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. phase jitter performance the phase jitter of the pll is defined as the variati ons in the skew between the falling edges of extal and the internal dsp clock for a given device in sp ecific temperature, voltage , input frequency and mf. these variations are a result of the pll locking m echanism. for input frequen cies greater than 15 mhz imips ? imhz ? i typf2 i typf1 ? () f2 f1 ? () ? ==
design considerations host port considerations motorola DSP56366 advance information 4-5 and mf 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. however, for mf < 10 and input frequencies greater than 10 mhz, this jitter is less than 2 ns. frequency jitter performance the frequency jitter of the pll is defi ned as the variation of the frequency of the internal dsp clock. for small mf (mf < 10) this jitter is sm aller than 0.5%. for mi d-range mf (10 < mf < 500) this jitter is between 0.5% and approximately 2%. for large mf (mf > 500), the frequency jitter is 2?3%. input (extal) jitter requirements the allowed jitter on the frequency of extal is 0.5%. if the rate of change of the frequency of extal is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme va lue for a long time), then the allowed jitter can be 2%. the phase and frequency jitter perform ance results are only valid if the input jitter is less than the prescribed values. host port considerations careful synchronization is requi red when reading multi-bit regist ers that are written by another asynchronous system. this synchronization is a co mmon problem when two asynchronous systems are connected, as they are in the host interface. the follo wing paragraphs present considerations for proper operation. host programming considerations ? unsynchronized reading of receive byte registers ?when reading the receive byte registers, receive register high (rxh), receive register midd le (rxm), or receive register low (rxl), the host interface programmer should use interrupts or poll the receive register data full (rxdf) flag that indicates whether data is ava ilable. this ensures that the data in the receive byte registers will be valid. ? overwriting transmit byte registers ?the host interface programme r should not write to the transmit byte registers, transmit register high (t xh), transmit register middle (txm), or transmit register low (txl), unless the transmit register da ta empty (txde) bit is set, indicating that the transmit byte registers are empty. this ensures that the transmit byte registers will transfer valid data to the host receive (hrx) register. ? synchronization of status bits from dsp to host ?hc, horeq , dma, hf3, hf2, trdy, txde, and rxdf status bits are set or cleared fro m inside the dsp and read by the host processor (refer to the user?s manual for desc riptions of these status bits). th e host can read these status bits
4-6 DSP56366 advance information motorola design considerations host port considerations very quickly without regard to the clock rate used by the dsp, but the state of the bit could be changing during the read operation. this is not ge nerally a system problem, because the bit will be read correctly in the next pass of any host polling routine. however, if the host asserts hen for more than timing number 31, with a minimum cycle time of timing number 31 + 32, th en these status bits are guaranteed to be stable. exercise care when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a sma ll probability that the host could read the bits during the transition and receiv e 01 or 10 instead of 11. if th e combination of hf3 and hf2 has significance, the host could read the wrong combination. therefor e, read the bits twice and check for consensus. ? overwriting the host vector ?the host interface programmer should change the host vector (hv) register only when the host command (hc) bit is clear. this ensures that the dsp interrupt control logic will receive a stable vector. ? cancelling a pending ho st command exception ?the host processor may elect to clear the hc bit to cancel the host command exception request at any time before it is recognized by the dsp. because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline dela ys), the dsp may execu te the host command exception after the hc bit is cleared. for these reas ons, the hv bits must not be changed at the same time that the hc bit is cleared. ? variance in the host interface timing ?the host interface (hdi) ma y vary (e.g. due to the pll lock time at reset). therefore, a host which attemp ts to load (bootstrap) the dsp should first make sure that the part has completed its hi port programming (e.g., by setting the init bit in icr then polling it and waiting it to be cleared, then reading the isr or by writing the treq/rreq together with the init and then polling init, isr, and the horeq pin). dsp programming considerations ? synchronization of status bits from host to dsp ?dma, hf1, hf0, hcp, htde, and hrdf status bits are set or cleared by the host processor side of the interface. these bits are individually synchronized to the dsp clock. (refer to the user?s manual for descriptions of these status bits.) ? reading hf0 and hf1 as an encoded pair ?care must be exercised when reading status bits hf0 and hf1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). a very small proba bility exists that the dsp will r ead the status bits synchronized during transition. therefore, hf0 and hf1 shou ld be read twice and checked for consensus.
motorola DSP56366 advance information 5-1 section 5 ordering information consult a motorola semiconductor sa les office or authorized distributor to determine product availability and to place an order. table 5-1 ordering information part supply voltage package type pin count frequency (mhz) order number DSP56366 3.3 v thin quad flat pack (tqfp) 144 120 xcd56366pv120 notes: 1. please consult the web site at www.dspaudio.motorola .com for current availability. 2. future products in the DSP56366 family may include other rom-based options. for additional information on future part development, or to request customer-s pecific rom-based support, call your local motorola semiconductor sales office or author ized distributor.
5-2 DSP56366 advance information motorola ordering information
motorola DSP56366 advance information a-1 appendix a power consumption benchmark the following benchmark program permits evaluation of dsp power usage in a test situation. it enables the pll, disables the external clock, and uses repeated multiply-accumulate instructions w ith a set of synthetic dsp applic ation data to emulate intensive sustained dsp operation. ;******************************************************************** ;******************************************************************** ;* ;* checks typical power consumption ;******************************************************************** page 200,55,0,0,0 nolist i_vec equ $000000 ; interrupt vectors for program debug only start equ $8000 ; main (external) program starting address int_prog equ $100 ; internal program memory starting address int_xdat equ $0 ; internal x-data memory starting address int_ydat equ $0 ; internal y-data memory starting address include "ioequ.asm" include "intequ.asm" list org p:start ; movep #$0123ff,x:m_bcr; bcr: area 3 : 1 w.s (sram) ; default: 1 w.s (sram) ; movep #$0d0000,x:m_pctl ; xtal disable ; pll enable ; clkout disable ; ; load the program ; move #int_prog,r0 move #prog_start,r1 do #(prog_end-prog_start),pload_loop move p:(r1)+,x0 move x0,p:(r0)+ nop pload_loop ; ; load the x-data ;
a-2 DSP56366 advance information motorola power consumption benchmark move #int_xdat,r0 move #xdat_start,r1 do #(xdat_end-xdat_start),xload_loop move p:(r1)+,x0 move x0,x:(r0)+ xload_loop ; ; load the y-data ; move #int_ydat,r0 move #ydat_start,r1 do #(ydat_end-ydat_start),yload_loop move p:(r1)+,x0 move x0,y:(r0)+ yload_loop ; jmp int_prog prog_start move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 ; clr a clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd ; sbr dor #60,_end mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end bra sbr nop nop nop nop prog_end nop nop xdat_start ; org x:0
power consumption benchmark motorola DSP56366 advance information a-3 dc $262eb9 dc $86f2fe dc $e56a5f dc $616cac dc $8ffd75 dc $9210a dc $a06d7b dc $cea798 dc $8dfbf1 dc $a063d6 dc $6c6657 dc $c2a544 dc $a3662d dc $a4e762 dc $84f0f3 dc $e6f1b0 dc $b3829 dc $8bf7ae dc $63a94f dc $ef78dc dc $242de5 dc $a3e0ba dc $ebab6b dc $8726c8 dc $ca361 dc $2f6e86 dc $a57347 dc $4be774 dc $8f349d dc $a1ed12 dc $4bfce3 dc $ea26e0 dc $cd7d99 dc $4ba85e dc $27a43f dc $a8b10c dc $d3a55 dc $25ec6a dc $2a255b dc $a5f1f8 dc $2426d1 dc $ae6536 dc $cbbc37 dc $6235a4 dc $37f0d dc $63bec2 dc $a5e4d3 dc $8ce810 dc $3ff09 dc $60e50e dc $cffb2f dc $40753c dc $8262c5
a-4 DSP56366 advance information motorola power consumption benchmark dc $ca641a dc $eb3b4b dc $2da928 dc $ab6641 dc $28a7e6 dc $4e2127 dc $482fd4 dc $7257d dc $e53c72 dc $1a8c3 dc $e27540 xdat_end ydat_start ; org y:0 dc $5b6da dc $c3f70b dc $6a39e8 dc $81e801 dc $c666a6 dc $46f8e7 dc $aaec94 dc $24233d dc $802732 dc $2e3c83 dc $a43e00 dc $c2b639 dc $85a47e dc $abfddf dc $f3a2c dc $2d7cf5 dc $e16a8a dc $ecb8fb dc $4bed18 dc $43f371 dc $83a556 dc $e1e9d7 dc $aca2c4 dc $8135ad dc $2ce0e2 dc $8f2c73 dc $432730 dc $a87fa9 dc $4a292e dc $a63ccf dc $6ba65c dc $e06d65 dc $1aa3a dc $a1b6eb dc $48ac48 dc $ef7ae1 dc $6e3006 dc $62f6c7
power consumption benchmark motorola DSP56366 advance information a-5 dc $6064f4 dc $87e41d dc $cb2692 dc $2c3863 dc $c6bc60 dc $43a519 dc $6139de dc $adf7bf dc $4b3e8c dc $6079d5 dc $e0f5ea dc $8230db dc $a3b778 dc $2bfe51 dc $e0a6b6 dc $68ffb7 dc $28f324 dc $8f2e8d dc $667842 dc $83e053 dc $a1fd90 dc $6b2689 dc $85b68e dc $622eaf dc $6162bc dc $e4a245 ydat_end
a-6 DSP56366 advance information motorola power consumption benchmark
motorola DSP56366 advance information b-1 appendix b ibis model [ibis ver] 2.1 [file name] 56366.ibs [file rev] 0.0 [date] 29/6/2000 [component] 56366 [manufacturer] motorola [package] |variable typ min max r_pkg 45m 22m 75m l_pkg 2.5nh 1.1nh 4.3nh c_pkg 1.3pf 1.2pf 1.4pf [pin]signal_name model_name 1 sck ip5b_io 2 ss_ ip5b_io 3 hreq_ ip5b_io 4 sdo0 ip5b_io 5 sdo1 ip5b_io 6 sdoi23 ip5b_io 7 sdoi32 ip5b_io 8 svcc power 9 sgnd gnd 10 sdoi41 ip5b_io 11 sdoi50 ip5b_io 12 fst ip5b_io 13 fsr ip5b_io 14 sckt ip5b_io 15 sckr ip5b_io 16 hsckt ip5b_io 17 hsckr ip5b_io 18 qvccl power 19 gnd gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 sgnd gnd 27 ado ip5b_io 28 aci ip5b_io 29 tio ip5b_io 30 hp13 ip5b_io 31 hp10 ip5b_io
b-2 DSP56366 advance information motorola ibis model 32 hp9 ip5b_io 33 hp8 ip5b_io 34 hp7 ip5b_io 35 hp6 ip5b_io 36 hp5 ip5b_io 37 hp4 ip5b_io 38 svcc power 39 sgnd gnd 40 hp3 ip5b_io 41 hp2 ip5b_io 42 hp1 ip5b_io 43 hp0 ip5b_io 44 ires_ ip5b_i 45 pvcc power 46 pcap power 47 pgnd gnd 48 sdo5 ipbw_io 49 qvcch power 50 fst_1 ipbw_io 51 aa2 icbc_o 52 cas_ icbc_o 53 sck_1 ipbw_io 54 qgnd gnd 55 cxtldis_ iexlh_i 56 qvccl power 57 cvcc power 58 cgnd gnd 59 fsr_1 ipbw_io 60 sckr1 ipbw_io 61 nmi_ ipbw_i 62 ta_ icbc_o 63 br_ icbc_o 64 bb_ icbc_o 65 cvcc power 66 cgnd gnd 67 wr_ icbc_o 68 rd_ icbc_o 69 aa1 icbc_o 70 aa0 icbc_o 71 bg_ icbc_o 72 eab0 icba_o 73 eab1 icba_o 74 avcc power 75 agnd gnd 76 eab2 icba_o 77 eab3 icba_o 78 eab4 icba_o 79 eab5 icba_o 80 avcc power 81 agnd gnd 82 eab6 icba_o 83 eab7 icba_o 84 eab8 icba_o
ibis model motorola DSP56366 advance information b-3 85 eab9 icba_o 86 avcc power 87 agnd gnd 88 eab10 icba_o 89 eab11 icba_o 90 qgnd gnd 91 qvcc power 92 eab12 icba_o 93 eab13 icba_o 94 eab14 icba_o 95 qvcch power 96 agnd gnd 97 eab15 icba_o 98 eab16 icba_o 99 eab17 icba_o 100 edb0 icba_io 101 edb1 icba_io 102 edb2 icba_io 103 dvcc power 104 dgnd gnd 105 edb3 icba_io 106 edb4 icba_io 107 edb5 icba_io 108 edb6 icba_io 109 edb7 icba_io 110 edb8 icba_io 111 dvcc power 112 dgnd gnd 113 edb9 icba_io 114 edb10 icba_io 115 edb11 icba_io 116 edb12 icba_io 117 edb13 icba_io 118 edb14 icba_io 119 dvcc power 120 dgnd gnd 121 edb15 icba_io 122 edb16 icba_io 123 edb17 icba_io 124 edb18 icba_io 125 edb19 icba_io 126 qvccl power 127 qgnd gnd 128 edb20 icba_io 129 dvcc power 130 dgnd gnd 131 edb21 icba_io 132 edb22 icba_io 133 edb23 icba_io 134 irqd_ ip5b_i 135 irqc_ ip5b_i 136 irqb_ ip5b_i 137 irqa_ ip5b_i
b-4 DSP56366 advance information motorola ibis model 138 sdo4_1 ip5b_io 139 tdo ip5b_o 140 tdi ip5b_i 141 tck ip5b_i 142 tms ip5b_i 143 mosi ip5b_io 144 sda ip5b_io | [model] ip5b_i model_type input polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | | [model] ip5b_io model_type i/o polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02
ibis model motorola DSP56366 advance information b-5 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00 -9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02 -7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02 -5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02 -3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02 -1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 | [pullup] |voltage i(typ) i(min) i(max)
b-6 DSP56366 advance information motorola ibis model | -3.30e+00 2.922e-04 2.177e-04 4.123e-04 -3.10e+00 2.881e-04 2.175e-04 4.021e-04 -2.90e+00 2.853e-04 2.173e-04 3.946e-04 -2.70e+00 2.836e-04 2.172e-04 3.893e-04 -2.50e+00 2.825e-04 2.171e-04 3.857e-04 -2.30e+00 2.819e-04 2.170e-04 3.834e-04 -2.10e+00 2.815e-04 2.169e-04 3.820e-04 -1.90e+00 2.813e-04 2.167e-04 3.812e-04 -1.70e+00 2.812e-04 2.520e-04 3.808e-04 -1.50e+00 2.811e-04 3.078e-02 3.806e-04 -1.30e+00 2.810e-04 2.684e-02 3.804e-04 -1.10e+00 2.809e-04 2.277e-02 3.802e-04 -9.00e-01 2.808e-04 1.864e-02 3.801e-04 -7.00e-01 2.997e-04 1.447e-02 3.799e-04 -5.00e-01 1.750e-02 1.031e-02 3.797e-04 -3.00e-01 1.048e-02 6.181e-03 3.776e-04 -1.00e-01 3.487e-03 2.084e-03 4.568e-03 1.000e-01 -3.40e-03 -2.03e-03 -4.22e-03 3.000e-01 -9.69e-03 -5.71e-03 -1.24e-02 5.000e-01 -1.52e-02 -8.99e-03 -1.95e-02 7.000e-01 -2.02e-02 -1.19e-02 -2.61e-02 9.000e-01 -2.46e-02 -1.43e-02 -3.21e-02 1.100e+00 -2.84e-02 -1.62e-02 -3.73e-02 1.300e+00 -3.14e-02 -1.77e-02 -4.18e-02 1.500e+00 -3.37e-02 -1.88e-02 -4.55e-02 1.700e+00 -3.55e-02 -1.95e-02 -4.85e-02 1.900e+00 -3.68e-02 -2.00e-02 -5.09e-02 2.100e+00 -3.78e-02 -2.04e-02 -5.27e-02 2.300e+00 -3.85e-02 -2.07e-02 -5.41e-02 2.500e+00 -3.91e-02 -2.10e-02 -5.51e-02 2.700e+00 -3.96e-02 -2.12e-02 -5.60e-02 2.900e+00 -4.01e-02 -2.15e-02 -5.67e-02 3.100e+00 -4.04e-02 -2.17e-02 -5.74e-02 3.300e+00 -4.08e-02 -2.18e-02 -5.79e-02 3.500e+00 -4.11e-02 -2.20e-02 -5.84e-02 3.700e+00 -4.14e-02 -2.78e-02 -5.89e-02 3.900e+00 -4.17e-02 -1.20e+00 -5.94e-02 4.100e+00 -4.32e-02 -2.15e+01 -5.98e-02 4.300e+00 -4.08e-01 -4.52e+01 -6.10e-02 4.500e+00 -2.73e+01 -6.89e+01 -6.84e-02 4.700e+00 -6.13e+01 -9.25e+01 -7.73e+00 4.900e+00 -9.54e+01 -1.17e+02 -4.18e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 |
ibis model motorola DSP56366 advance information b-7 [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dv/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [model] ip5b_o model_type 3-state polarity non-inverting c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01
b-8 DSP56366 advance information motorola ibis model -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00 -9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02 -7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02 -5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02 -3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02 -1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.922e-04 2.177e-04 4.123e-04 -3.10e+00 2.881e-04 2.175e-04 4.021e-04 -2.90e+00 2.853e-04 2.173e-04 3.946e-04 -2.70e+00 2.836e-04 2.172e-04 3.893e-04 -2.50e+00 2.825e-04 2.171e-04 3.857e-04 -2.30e+00 2.819e-04 2.170e-04 3.834e-04 -2.10e+00 2.815e-04 2.169e-04 3.820e-04 -1.90e+00 2.813e-04 2.167e-04 3.812e-04
ibis model motorola DSP56366 advance information b-9 -1.70e+00 2.812e-04 2.520e-04 3.808e-04 -1.50e+00 2.811e-04 3.078e-02 3.806e-04 -1.30e+00 2.810e-04 2.684e-02 3.804e-04 -1.10e+00 2.809e-04 2.277e-02 3.802e-04 -9.00e-01 2.808e-04 1.864e-02 3.801e-04 -7.00e-01 2.997e-04 1.447e-02 3.799e-04 -5.00e-01 1.750e-02 1.031e-02 3.797e-04 -3.00e-01 1.048e-02 6.181e-03 3.776e-04 -1.00e-01 3.487e-03 2.084e-03 4.568e-03 1.000e-01 -3.40e-03 -2.03e-03 -4.22e-03 3.000e-01 -9.69e-03 -5.71e-03 -1.24e-02 5.000e-01 -1.52e-02 -8.99e-03 -1.95e-02 7.000e-01 -2.02e-02 -1.19e-02 -2.61e-02 9.000e-01 -2.46e-02 -1.43e-02 -3.21e-02 1.100e+00 -2.84e-02 -1.62e-02 -3.73e-02 1.300e+00 -3.14e-02 -1.77e-02 -4.18e-02 1.500e+00 -3.37e-02 -1.88e-02 -4.55e-02 1.700e+00 -3.55e-02 -1.95e-02 -4.85e-02 1.900e+00 -3.68e-02 -2.00e-02 -5.09e-02 2.100e+00 -3.78e-02 -2.04e-02 -5.27e-02 2.300e+00 -3.85e-02 -2.07e-02 -5.41e-02 2.500e+00 -3.91e-02 -2.10e-02 -5.51e-02 2.700e+00 -3.96e-02 -2.12e-02 -5.60e-02 2.900e+00 -4.01e-02 -2.15e-02 -5.67e-02 3.100e+00 -4.04e-02 -2.17e-02 -5.74e-02 3.300e+00 -4.08e-02 -2.18e-02 -5.79e-02 3.500e+00 -4.11e-02 -2.20e-02 -5.84e-02 3.700e+00 -4.14e-02 -2.78e-02 -5.89e-02 3.900e+00 -4.17e-02 -1.20e+00 -5.94e-02 4.100e+00 -4.32e-02 -2.15e+01 -5.98e-02 4.300e+00 -4.08e-01 -4.52e+01 -6.10e-02 4.500e+00 -2.73e+01 -6.89e+01 -6.84e-02 4.700e+00 -6.13e+01 -9.25e+01 -7.73e+00 4.900e+00 -9.54e+01 -1.17e+02 -4.18e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02
b-10 DSP56366 advance information motorola ibis model -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dv/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [model] icba_io model_type i/o polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03
ibis model motorola DSP56366 advance information b-11 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 2.500e+00 1.440e-01 7.098e-02 1.958e-01 2.700e+00 1.445e-01 7.128e-02 1.970e-01 2.900e+00 1.450e-01 7.154e-02 1.979e-01 3.100e+00 1.454e-01 7.176e-02 1.986e-01 3.300e+00 1.458e-01 7.196e-02 1.993e-01 3.500e+00 1.461e-01 7.223e-02 1.999e-01 3.700e+00 1.464e-01 8.810e-02 2.004e-01 3.900e+00 1.469e-01 2.589e+00 2.009e-01 4.100e+00 1.490e-01 1.451e+01 2.015e-01 4.300e+00 1.501e+00 2.658e+01 2.030e-01 4.500e+00 1.813e+01 3.866e+01 2.385e-01 4.700e+00 3.540e+01 5.076e+01 9.563e+00 4.900e+00 5.269e+01 6.461e+01 2.682e+01 5.100e+00 7.541e+01 8.261e+01 4.409e+01 5.300e+00 1.012e+02 1.006e+02 6.258e+01 5.500e+00 1.270e+02 1.186e+02 8.836e+01 5.700e+00 1.527e+02 1.366e+02 1.141e+02 5.900e+00 1.785e+02 1.546e+02 1.399e+02 6.100e+00 2.043e+02 1.726e+02 1.657e+02 6.300e+00 2.301e+02 1.906e+02 1.915e+02 6.500e+00 2.559e+02 2.086e+02 2.173e+02 6.600e+00 2.688e+02 2.176e+02 2.302e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.237e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.360e+00 1.444e+01 9.362e+00 -9.00e-01 4.275e-02 2.518e+00 4.663e-02 -7.00e-01 8.208e-03 2.012e-02 1.070e-02 -5.00e-01 5.635e-03 3.518e-03 7.068e-03
b-12 DSP56366 advance information motorola ibis model -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03 3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03 5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03 7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03 9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02 1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02 1.300e+00 -1.03e-02 -6.55e-02 -1.38e-02 1.500e+00 -1.25e-01 -6.93e-02 -1.70e-01 1.700e+00 -1.31e-01 -7.19e-02 -1.82e-01 1.900e+00 -1.36e-01 -7.38e-02 -1.91e-01 2.100e+00 -1.40e-01 -7.53e-02 -1.97e-01 2.300e+00 -1.42e-01 -7.65e-02 -2.03e-01 2.500e+00 -1.44e-01 -7.76e-02 -2.07e-01 2.700e+00 -1.46e-01 -7.85e-02 -2.10e-01 2.900e+00 -1.48e-01 -7.93e-02 -2.13e-01 3.100e+00 -1.49e-01 -8.00e-02 -2.15e-01 3.300e+00 -1.50e-01 -8.06e-02 -2.17e-01 3.500e+00 -1.52e-01 -8.13e-02 -2.19e-01 3.700e+00 -1.53e-01 -8.84e-02 -2.21e-01 3.900e+00 -1.54e-01 -1.26e+00 -2.22e-01 4.100e+00 -1.57e-01 -2.16e+01 -2.24e-01 4.300e+00 -5.25e-01 -4.53e+01 -2.27e-01 4.500e+00 -2.74e+01 -6.89e+01 -2.38e-01 4.700e+00 -6.14e+01 -9.26e+01 -7.90e+00 4.900e+00 -9.55e+01 -1.17e+02 -4.20e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.60e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02
ibis model motorola DSP56366 advance information b-13 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dv/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [model] icba_o model_type 3-state polarity non-inverting c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02
b-14 DSP56366 advance information motorola ibis model -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 2.500e+00 1.440e-01 7.098e-02 1.958e-01 2.700e+00 1.445e-01 7.128e-02 1.970e-01 2.900e+00 1.450e-01 7.154e-02 1.979e-01 3.100e+00 1.454e-01 7.176e-02 1.986e-01 3.300e+00 1.458e-01 7.196e-02 1.993e-01 3.500e+00 1.461e-01 7.223e-02 1.999e-01 3.700e+00 1.464e-01 8.810e-02 2.004e-01 3.900e+00 1.469e-01 2.589e+00 2.009e-01 4.100e+00 1.490e-01 1.451e+01 2.015e-01 4.300e+00 1.501e+00 2.658e+01 2.030e-01 4.500e+00 1.813e+01 3.866e+01 2.385e-01 4.700e+00 3.540e+01 5.076e+01 9.563e+00 4.900e+00 5.269e+01 6.461e+01 2.682e+01 5.100e+00 7.541e+01 8.261e+01 4.409e+01 5.300e+00 1.012e+02 1.006e+02 6.258e+01 5.500e+00 1.270e+02 1.186e+02 8.836e+01 5.700e+00 1.527e+02 1.366e+02 1.141e+02 5.900e+00 1.785e+02 1.546e+02 1.399e+02 6.100e+00 2.043e+02 1.726e+02 1.657e+02 6.300e+00 2.301e+02 1.906e+02 1.915e+02 6.500e+00 2.559e+02 2.086e+02 2.173e+02 6.600e+00 2.688e+02 2.176e+02 2.302e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02
ibis model motorola DSP56366 advance information b-15 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.237e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.360e+00 1.444e+01 9.362e+00 -9.00e-01 4.275e-02 2.518e+00 4.663e-02 -7.00e-01 8.208e-03 2.012e-02 1.070e-02 -5.00e-01 5.635e-03 3.518e-03 7.068e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03 3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03 5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03 7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03 9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02 1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02 1.300e+00 -1.03e-02 -6.55e-02 -1.38e-02 1.500e+00 -1.25e-01 -6.93e-02 -1.70e-01 1.700e+00 -1.31e-01 -7.19e-02 -1.82e-01 1.900e+00 -1.36e-01 -7.38e-02 -1.91e-01 2.100e+00 -1.40e-01 -7.53e-02 -1.97e-01 2.300e+00 -1.42e-01 -7.65e-02 -2.03e-01 2.500e+00 -1.44e-01 -7.76e-02 -2.07e-01 2.700e+00 -1.46e-01 -7.85e-02 -2.10e-01 2.900e+00 -1.48e-01 -7.93e-02 -2.13e-01 3.100e+00 -1.49e-01 -8.00e-02 -2.15e-01 3.300e+00 -1.50e-01 -8.06e-02 -2.17e-01 3.500e+00 -1.52e-01 -8.13e-02 -2.19e-01 3.700e+00 -1.53e-01 -8.84e-02 -2.21e-01 3.900e+00 -1.54e-01 -1.26e+00 -2.22e-01 4.100e+00 -1.57e-01 -2.16e+01 -2.24e-01 4.300e+00 -5.25e-01 -4.53e+01 -2.27e-01 4.500e+00 -2.74e+01 -6.89e+01 -2.38e-01 4.700e+00 -6.14e+01 -9.26e+01 -7.90e+00 4.900e+00 -9.55e+01 -1.17e+02 -4.20e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.60e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) |
b-16 DSP56366 advance information motorola ibis model -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dv/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [model] icbc_o
ibis model motorola DSP56366 advance information b-17 model_type 3-state polarity non-inverting c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -2.51e-02 -1.18e+00 -2.65e-02 -7.00e-01 -1.30e-02 -1.16e-02 -1.58e-02 -5.00e-01 -9.33e-03 -4.67e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 9.632e-02 4.783e-02 2.331e-02 1.700e+00 1.012e-01 4.994e-02 1.302e-01 1.900e+00 1.039e-01 5.118e-02 1.369e-01 2.100e+00 1.053e-01 5.184e-02 1.412e-01 2.300e+00 1.060e-01 5.223e-02 1.436e-01 2.500e+00 1.065e-01 5.251e-02 1.449e-01 2.700e+00 1.069e-01 5.274e-02 1.458e-01 2.900e+00 1.073e-01 5.293e-02 1.464e-01 3.100e+00 1.076e-01 5.309e-02 1.470e-01 3.300e+00 1.078e-01 5.324e-02 1.475e-01 3.500e+00 1.081e-01 5.344e-02 1.479e-01 3.700e+00 1.083e-01 6.705e-02 1.483e-01 3.900e+00 1.086e-01 2.529e+00 1.487e-01 4.100e+00 1.103e-01 1.438e+01 1.491e-01 4.300e+00 1.437e+00 2.638e+01 1.503e-01 4.500e+00 1.800e+01 3.839e+01 1.810e-01 4.700e+00 3.519e+01 5.041e+01 9.452e+00 4.900e+00 5.241e+01 6.419e+01 2.664e+01 5.100e+00 7.505e+01 8.210e+01 4.384e+01 5.300e+00 1.007e+02 1.000e+02 6.224e+01
b-18 DSP56366 advance information motorola ibis model 5.500e+00 1.264e+02 1.179e+02 8.794e+01 5.700e+00 1.522e+02 1.359e+02 1.136e+02 5.900e+00 1.779e+02 1.538e+02 1.394e+02 6.100e+00 2.036e+02 1.717e+02 1.651e+02 6.300e+00 2.293e+02 1.896e+02 1.908e+02 6.500e+00 2.550e+02 2.075e+02 2.165e+02 6.600e+00 2.678e+02 2.165e+02 2.293e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.677e+02 1.896e+02 2.677e+02 -3.10e+00 2.420e+02 1.716e+02 2.420e+02 -2.90e+00 2.163e+02 1.537e+02 2.163e+02 -2.70e+00 1.906e+02 1.358e+02 1.906e+02 -2.50e+00 1.649e+02 1.179e+02 1.649e+02 -2.30e+00 1.392e+02 9.996e+01 1.392e+02 -2.10e+00 1.135e+02 8.205e+01 1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.302e+00 1.433e+01 9.303e+00 -9.00e-01 3.838e-02 2.477e+00 4.183e-02 -7.00e-01 8.115e-03 1.789e-02 1.045e-02 -5.00e-01 5.634e-03 3.503e-03 7.064e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 1.000e-01 -1.09e-03 -6.56e-04 -1.38e-03 3.000e-01 -3.12e-03 -1.86e-03 -3.99e-03 5.000e-01 -4.96e-03 -2.93e-03 -6.39e-03 7.000e-01 -6.60e-03 -3.87e-03 -8.59e-03 9.000e-01 -8.04e-03 -4.66e-03 -1.06e-02 1.100e+00 -9.26e-03 -5.30e-03 -1.23e-02 1.300e+00 -1.03e-02 -4.75e-02 -1.41e-02 1.500e+00 -9.03e-02 -5.02e-02 -1.23e-01 1.700e+00 -9.49e-02 -5.21e-02 -1.31e-01 1.900e+00 -9.84e-02 -5.34e-02 -1.38e-01 2.100e+00 -1.01e-01 -5.45e-02 -1.43e-01 2.300e+00 -1.03e-01 -5.54e-02 -1.47e-01 2.500e+00 -1.05e-01 -5.62e-02 -1.50e-01 2.700e+00 -1.06e-01 -5.68e-02 -1.52e-01 2.900e+00 -1.07e-01 -5.74e-02 -1.54e-01 3.100e+00 -1.08e-01 -5.79e-02 -1.56e-01 3.300e+00 -1.09e-01 -5.84e-02 -1.57e-01 3.500e+00 -1.10e-01 -5.89e-02 -1.59e-01 3.700e+00 -1.11e-01 -6.49e-02 -1.60e-01 3.900e+00 -1.11e-01 -1.23e+00 -1.61e-01 4.100e+00 -1.14e-01 -2.16e+01 -1.62e-01 4.300e+00 -4.76e-01 -4.52e+01 -1.64e-01 4.500e+00 -2.73e+01 -6.89e+01 -1.73e-01 4.700e+00 -6.14e+01 -9.25e+01 -7.82e+00 4.900e+00 -9.54e+01 -1.17e+02 -4.19e+01
ibis model motorola DSP56366 advance information b-19 5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.20e+02 -4.18e+02 -4.41e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -1.03e-02 -1.17e+00 -9.27e-03 -7.00e-01 -3.74e-04 -5.73e-03 -1.14e-03 -5.00e-01 -1.72e-06 -5.06e-05 -1.28e-05 -3.00e-01 -1.67e-09 -4.65e-07 -1.10e-08 -1.00e-01 -2.03e-11 -4.80e-09 -2.71e-11 0.000e+00 -1.69e-11 -1.61e-09 -1.89e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.677e+02 1.896e+02 2.677e+02 -3.10e+00 2.420e+02 1.716e+02 2.420e+02 -2.90e+00 2.163e+02 1.537e+02 2.163e+02 -2.70e+00 1.906e+02 1.358e+02 1.906e+02 -2.50e+00 1.649e+02 1.179e+02 1.649e+02 -2.30e+00 1.392e+02 9.996e+01 1.392e+02 -2.10e+00 1.135e+02 8.205e+01 1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.300e+00 1.433e+01 9.301e+00 -9.00e-01 2.962e-02 2.475e+00 3.075e-02 -7.00e-01 2.501e-04 1.354e-02 6.708e-04 -5.00e-01 2.066e-06 6.280e-05 1.204e-05 -3.00e-01 2.487e-09 5.128e-07 1.417e-08 -1.00e-01 5.672e-11 5.639e-09 6.832e-11 0.000e+00 5.334e-11 1.992e-09 5.783e-11
b-20 DSP56366 advance information motorola ibis model | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.570/0.200 1.210/0.411 1.810/0.149 | | dv/dt_f 1.590/0.304 1.170/0.673 1.800/0.205 | | [model] ipbw_i model_type input polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04 -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02
ibis model motorola DSP56366 advance information b-21 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | | [model] ipbw_io model_type i/o polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [pulldown] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -3.69e-02 -1.17e+00 -3.79e-02 -7.00e-01 -2.52e-02 -1.67e-02 -2.81e-02 -5.00e-01 -1.83e-02 -9.77e-03 -2.04e-02 -3.00e-01 -1.11e-02 -5.89e-03 -1.24e-02 -1.00e-01 -3.77e-03 -1.98e-03 -4.20e-03 1.000e-01 3.729e-03 1.940e-03 4.177e-03 3.000e-01 1.076e-02 5.578e-03 1.216e-02 5.000e-01 1.723e-02 8.907e-03 1.965e-02 7.000e-01 2.311e-02 1.191e-02 2.663e-02 9.000e-01 2.836e-02 1.455e-02 3.305e-02 1.100e+00 3.292e-02 1.680e-02 3.887e-02 1.300e+00 3.675e-02 1.862e-02 4.404e-02 1.500e+00 3.979e-02 1.997e-02 4.850e-02 1.700e+00 4.205e-02 2.085e-02 5.223e-02 1.900e+00 4.347e-02 2.136e-02 5.518e-02 2.100e+00 4.413e-02 2.162e-02 5.728e-02
b-22 DSP56366 advance information motorola ibis model 2.300e+00 4.445e-02 2.176e-02 5.843e-02 2.500e+00 4.465e-02 2.186e-02 5.899e-02 2.700e+00 4.479e-02 2.194e-02 5.931e-02 2.900e+00 4.492e-02 2.200e-02 5.953e-02 3.100e+00 4.502e-02 2.206e-02 5.971e-02 3.300e+00 4.511e-02 2.211e-02 5.986e-02 3.500e+00 4.519e-02 2.219e-02 5.999e-02 3.700e+00 4.526e-02 3.324e-02 6.010e-02 3.900e+00 4.536e-02 2.452e+00 6.021e-02 4.100e+00 4.614e-02 1.423e+01 6.032e-02 4.300e+00 1.344e+00 2.615e+01 6.065e-02 4.500e+00 1.783e+01 3.808e+01 8.548e-02 4.700e+00 3.495e+01 5.001e+01 9.298e+00 4.900e+00 5.208e+01 6.371e+01 2.640e+01 5.100e+00 7.463e+01 8.154e+01 4.352e+01 5.300e+00 1.002e+02 9.937e+01 6.184e+01 5.500e+00 1.259e+02 1.172e+02 8.745e+01 5.700e+00 1.515e+02 1.350e+02 1.131e+02 5.900e+00 1.771e+02 1.529e+02 1.387e+02 6.100e+00 2.027e+02 1.707e+02 1.643e+02 6.300e+00 2.283e+02 1.885e+02 1.899e+02 6.500e+00 2.539e+02 2.064e+02 2.155e+02 6.600e+00 2.667e+02 2.153e+02 2.283e+02 | [pullup] |voltage i(typ) i(min) i(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.635e+01 2.613e+01 2.635e+01 -1.10e+00 9.243e+00 1.421e+01 9.245e+00 -9.00e-01 5.536e-02 2.435e+00 6.260e-02 -7.00e-01 2.847e-02 2.689e-02 3.437e-02 -5.00e-01 2.025e-02 1.265e-02 2.451e-02 -3.00e-01 1.208e-02 7.503e-03 1.467e-02 -1.00e-01 3.994e-03 2.474e-03 4.868e-03 1.000e-01 -3.88e-03 -2.38e-03 -4.76e-03 3.000e-01 -1.11e-02 -6.76e-03 -1.37e-02 5.000e-01 -1.76e-02 -1.06e-02 -2.20e-02 7.000e-01 -2.35e-02 -1.40e-02 -2.95e-02 9.000e-01 -2.86e-02 -1.69e-02 -3.63e-02 1.100e+00 -3.30e-02 -1.93e-02 -4.23e-02 1.300e+00 -3.65e-02 -2.10e-02 -4.75e-02 1.500e+00 -3.92e-02 -2.22e-02 -5.17e-02 1.700e+00 -4.12e-02 -2.29e-02 -5.51e-02
ibis model motorola DSP56366 advance information b-23 1.900e+00 -4.26e-02 -2.35e-02 -5.77e-02 2.100e+00 -4.36e-02 -2.38e-02 -5.97e-02 2.300e+00 -4.43e-02 -2.42e-02 -6.11e-02 2.500e+00 -4.49e-02 -2.44e-02 -6.22e-02 2.700e+00 -4.54e-02 -2.47e-02 -6.31e-02 2.900e+00 -4.58e-02 -2.49e-02 -6.38e-02 3.100e+00 -4.61e-02 -2.50e-02 -6.44e-02 3.300e+00 -4.65e-02 -2.52e-02 -6.49e-02 3.500e+00 -4.68e-02 -2.54e-02 -6.54e-02 3.700e+00 -4.70e-02 -2.99e-02 -6.58e-02 3.900e+00 -4.73e-02 -1.19e+00 -6.62e-02 4.100e+00 -4.81e-02 -2.15e+01 -6.66e-02 4.300e+00 -4.00e-01 -4.51e+01 -6.72e-02 4.500e+00 -2.72e+01 -6.87e+01 -7.21e-02 4.700e+00 -6.12e+01 -9.24e+01 -7.70e+00 4.900e+00 -9.52e+01 -1.17e+02 -4.17e+01 5.100e+00 -1.37e+02 -1.52e+02 -7.57e+01 5.300e+00 -1.88e+02 -1.88e+02 -1.10e+02 5.500e+00 -2.39e+02 -2.23e+02 -1.60e+02 5.700e+00 -2.90e+02 -2.58e+02 -2.11e+02 5.900e+00 -3.41e+02 -2.94e+02 -2.62e+02 6.100e+00 -3.92e+02 -3.29e+02 -3.13e+02 6.300e+00 -4.43e+02 -3.65e+02 -3.64e+02 6.500e+00 -4.94e+02 -4.00e+02 -4.15e+02 6.600e+00 -5.20e+02 -4.18e+02 -4.41e+02 | [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04 -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02
b-24 DSP56366 advance information motorola ibis model -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | [ramp] r_load = 50.00 |voltage i(typ) i(min) i(max) | | dv/dt_r 1.140/0.494 0.699/0.978 1.400/0.354 | | dv/dt_f 1.150/0.505 0.642/0.956 1.350/0.350 | | [model] iexlh_i model_type input polarity non-inverting vinl= 0.8000v vinh= 2.000v c_comp 5.00pf 5.00pf 5.00pf | | [voltage range] 3.3v 3v 3.6v [gnd_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 -5.21e+02 -3.66e+02 -5.18e+02 -3.10e+00 -4.70e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02 -2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02 -2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02 -2.10e+00 -2.15e+02 -1.53e+02 -2.12e+02 -1.90e+00 -1.64e+02 -1.18e+02 -1.61e+02 -1.70e+00 -1.14e+02 -9.34e+01 -1.11e+02 -1.50e+00 -7.93e+01 -6.98e+01 -7.68e+01 -1.30e+00 -4.53e+01 -4.62e+01 -4.28e+01 -1.10e+00 -1.13e+01 -2.26e+01 -8.78e+00 -9.00e-01 -7.94e-03 -1.87e+00 -3.77e-03
ibis model motorola DSP56366 advance information b-25 -7.00e-01 -1.62e-06 -5.11e-03 -7.69e-07 -5.00e-01 -3.45e-10 -1.40e-05 -1.72e-10 -3.00e-01 -1.29e-11 -3.90e-08 -1.38e-11 -1.00e-01 -1.10e-11 -8.67e-10 -1.19e-11 0.000e+00 -1.01e-11 -7.13e-10 -1.10e-11 | [power_clamp] |voltage i(typ) i(min) i(max) | -3.30e+00 2.653e+02 1.870e+02 2.653e+02 -3.10e+00 2.398e+02 1.693e+02 2.398e+02 -2.90e+00 2.143e+02 1.516e+02 2.143e+02 -2.70e+00 1.888e+02 1.339e+02 1.888e+02 -2.50e+00 1.633e+02 1.162e+02 1.633e+02 -2.30e+00 1.378e+02 9.847e+01 1.378e+02 -2.10e+00 1.123e+02 8.076e+01 1.123e+02 -1.90e+00 8.682e+01 6.305e+01 8.682e+01 -1.70e+00 6.133e+01 4.947e+01 6.133e+01 -1.50e+00 4.313e+01 3.766e+01 4.313e+01 -1.30e+00 2.614e+01 2.585e+01 2.614e+01 -1.10e+00 9.145e+00 1.404e+01 9.145e+00 -9.00e-01 1.797e-02 2.364e+00 1.797e-02 -7.00e-01 3.667e-06 7.589e-03 3.667e-06 -5.00e-01 7.730e-10 2.072e-05 7.748e-10 -3.00e-01 2.293e-11 5.767e-08 2.476e-11 -1.00e-01 2.096e-11 1.163e-09 2.278e-11 0.000e+00 2.004e-11 9.618e-10 2.186e-11 | [end]
b-26 DSP56366 advance information motorola ibis model
how to reach us: usa/europe/locat ions not listed : motorola literature distribution p.o. box 5405 denver, colorado 80217 1 (800) 441-2447 1 (303) 675-2140 asia/pacific : motorola semiconductors h.k. ltd. 8b tai ping industrial park 51 ting kok road tai po, n.t., hong kong 852-26629298 technical resource center: 1 (800) 521-6274 dsp helpline dsphelp@dsp.sps.mot.com japan : nippon motorola ltd. spd, strategic planning office 4-32-1, nishi- gotanda shinagawa-ku, tokyo 141, japan 81-3-5487-8488 internet : http://dspaudio.motorola.com symphony and once are registered trademarks of motorola, inc. motorola reserves the right to make ch anges without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the su itability of its products fo r any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation conse quential or incidental damages. ?typical? pa rameters which may be provided in motorola data sheets and/ or specifications can and do vary in diffe rent applications and actual performance may vary over time. all operating parameters , including ?typicals? must be vali dated for each customer application by customer ?s technical experts. motorola does not convey any license under its patent rights nor the ri ghts of others. motorola products are not designed, intended, or authorized for u se as components in systems intended for surgical implant into the body, or ot her applications intended to support life, or for any o ther application in which the failure of the mo torola product could create a situation wher e personal injury or death may occur. sho uld buyer purchase or use motorola products fo r any such unintended or unauthorized ap plication, buyer shal l indemnify and hold motorola and its officers, empl oyees, subsidiaries, affi liates, and distributors harmless agai nst all claims, co sts, damages, a nd expenses, and reasonable attorney fees arising out of, dire ctly or indirectly, any claim of pe rsonal injury or death associated with such unintended or unauthorized us e, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and b are registered trademarks of motorola, inc. motoro la, inc. is an equal oppor tunity/affirmative action employer.

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